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Jagannathan Bharath

from Laguna Niguel, CA
Age ~64
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Also known as:
Jagannatha Bharath, Jaganna Bharath, Jagannath Bharath, Bharath Jagannathan, N Bharath
Phone and address:
25461 Englewood Dr, Laguna Beach, CA 92677
Related to:
Naomi J Bharath, 29Priya Bharath, 57
Connected to:
Amrith Bharath, 44Harshal Bharatia, 37Jawahar Bharathram, 39Krishna S Bharathala, 28Marimuthu Bharathiraja, 46Prakash Bharathy, 40Purabi Bharatiya, 78Rekha D Bharatia, 72Samara N Bharath, 29Sumeet K Bharati, 46

Jagannathan Bharath Phones & Addresses

  • 25461 Englewood Dr, Laguna Niguel, CA 92677
  • 29841 White Otter Ln, Laguna Niguel, CA 92677 (916) 933-8593
  • 2521 Stratford Cir, El Dorado Hills, CA 95762 (916) 933-8593
  • Folsom, CA
  • Austin, TX
  • El Dorado Hls, CA
  • 25461 Englewood Dr, Laguna Niguel, CA 92677 (916) 933-8593

Work

Position: Healthcare Support Occupations

Education

Degree: High school graduate or higher

Public records

Vehicle Records

Jagannathan Bharath

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Address:
29841 White Otter Ln, Laguna Niguel, CA 92677
Phone:
(916) 933-8593
VIN:
WMWSV3C5XCTY19830
Make:
MINI
Model:
COOPER
Year:
2012

Resumes

Resumes

Jagannathan Bharath Photo 1

Jagannathan Bharath

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Jagannathan Bharath
Director - Marketing
Clariphy Communications Inc
Cell Phone Service · All Other Specialty Trade Contractors
16 Technology Dr, Irvine, CA 92618
(949) 861-3074, (949) 922-8658

Publications

Us Patents

Method And Apparatus For Accessing Variable Sized Blocks Of Data

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US Patent:
20030058883, Mar 27, 2003
Filed:
Sep 30, 2002
Appl. No.:
10/261126
Inventors:
David Larson - Austin TX, US
Jagannathan Bharath - Folsom CA, US
Assignee:
Legerity, Inc.
International Classification:
H04L012/66
G06F015/16
US Classification:
370/463000, 709/250000
Abstract:
A method and apparatus are provided for accessing data. The method includes defining a first portion of a memory for receiving data and providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data. The method further includes transferring a portion of data from the source to the first portion of the memory, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory.

System And Method For Bit Interleaving Of Half-Rate Speech Data

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US Patent:
60354348, Mar 7, 2000
Filed:
Jun 12, 1997
Appl. No.:
8/873941
Inventors:
Sharif M. Sazzad - North Brunswick NJ
Jagannathan Bharath - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1100
US Classification:
714776
Abstract:
A memory-efficient system and method for generating data blocks "on demand" for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded half-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

System And Method For Bit Interleaving Of Full-Rate Speech Data

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US Patent:
63245043, Nov 27, 2001
Filed:
May 26, 2000
Appl. No.:
9/580654
Inventors:
Sharif M. Sazzad - North Brunswick NJ
Jagannathan Bharath - Austin TX
Tony E. Sawan - Austin TX
Assignee:
Legerity, Inc. - Austin TX
International Classification:
G10L 1902
US Classification:
704229
Abstract:
A memory-efficient system and method for generating data blocks "on demand" for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

System And Method For Bit Interleaving Of Full-Rate Speech Data

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US Patent:
61014656, Aug 8, 2000
Filed:
Jun 12, 1997
Appl. No.:
8/873625
Inventors:
Sharif M. Sazzad - North Brunswick NJ
Jagannathan Bharath - Austin TX
Tony E. Sawan - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G10L 1900
US Classification:
704229
Abstract:
A memory-efficient system and method for generating data blocks "on demand" for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.
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Jagannathan Bharath from Laguna Niguel, CA, age ~64 Get Report