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John Surowka Phones & Addresses

  • 50 Front St, Binghamton, NY 13905 (607) 723-6032
  • 50 Front St, Binghamton, NY 13905 (607) 857-1358

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: Associate degree or higher

Publications

Us Patents

Method For Reducing Coefficient Of Thermal Expansion In Chip Attach Packages

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US Patent:
6387830, May 14, 2002
Filed:
Mar 10, 1999
Appl. No.:
09/265210
Inventors:
Lawrence Robert Blumberg - Johnson City NY
Robert Maynard Japp - Vestal NY
William John Rudik - Vestal NY
John Frank Surowka - Binghamton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B32B 526
US Classification:
442103, 29832, 442180, 442247, 442251, 442255
Abstract:
A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0. 05% to 0. 3%, preferably from about 0. 08% to 0. 10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably not B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

Method For Reducing Coefficient Of Thermal Expansion In Chip Attach Packages

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US Patent:
6586352, Jul 1, 2003
Filed:
Oct 20, 2000
Appl. No.:
09/693766
Inventors:
Lawrence Robert Blumberg - Johnson City NY
Robert Maynard Japp - Vestal NY
William John Rudik - Vestal NY
John Frank Surowka - Binghamton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B32B 2709
US Classification:
442181, 442103, 442247, 442255, 29832
Abstract:
A simple, inexpensive, drillable, reduced CTE laminate and circuitized structure comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0. 05% to 0. 3%, preferably from about 0. 08% to 0. 10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. The method further comprises providing a resin volume percent, woven glass cloth volume percent and metal volume percent of the circuitized structure to be fabricated; selecting a desired CTE for the circuitized structure to be fabricated; and determining the amount of non-woven quartz or non-woven glass mat to be incorporated according to a formula.

Method For Reducing Coefficient Of Thermal Expansion In Chip Attach Packages

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US Patent:
6841026, Jan 11, 2005
Filed:
Mar 26, 2002
Appl. No.:
10/107112
Inventors:
Lawrence Robert Blumberg - Johnson City NY, US
Robert Maynard Japp - Vestal NY, US
William John Rudik - Vestal NY, US
John Frank Surowka - Binghamton NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B32B 3104
US Classification:
156285, 156166, 442103, 442180, 442247, 442251, 442255, 442252, 442253, 442262
Abstract:
A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. One embodiment of the reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0. 05% to 0. 3%, preferably from about 0. 08% to 0. 10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat.

Method For Reducing Coefficient Of Thermal Expansion In Chip Attach Packages

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US Patent:
61367338, Oct 24, 2000
Filed:
Jun 13, 1997
Appl. No.:
8/874902
Inventors:
Lawrence Robert Blumberg - Johnson City NY
Robert Maynard Japp - Vestal NY
William John Rudik - Vestal NY
John Frank Surowka - Binghamton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B32B 526
C09J 502
US Classification:
442247
Abstract:
A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0. 05% to 0. 3%, preferably from about 0. 08% to 0. 10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

Laminated Electroplating Rack And Connection System For Optimized Plating

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US Patent:
61769851, Jan 23, 2001
Filed:
Oct 23, 1998
Appl. No.:
9/178084
Inventors:
Francis J. Downes - Vestal NY
Raymond Thomas Galasco - Vestal NY
Robert Maynard Japp - Vestal NY
John Frank Surowka - Binghamton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C25D 1704
US Classification:
2042971
Abstract:
An electroplating apparatus provides high current electrical connections in a small area to a workpiece. The contact area may use a dendrite surface to improve the connection. An insulative gasket prevents electroplating fluids from entering the region about the contact area. A heavy core laminated within a supporting structure provides uniform current distribution of high electrical currents to the dendrite covered contact areas.
John Surowka from Binghamton, NY, age ~85 Get Report