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Jordan S Plofsky

from Chicago, IL
Age ~63
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Also known as:
Jordan P Plofsky, Jordon S Plofsky, Jordon J Plofsky, Jordan Plosky, Plofsky Jordon, Plofsky Jordan, Plonowski Jordon, Poo Ploi, Phat Loi
Phone and address:
415 North Water St APT 2506, Chicago, IL 60611
(312) 854-3803
Related to:
William L Mylan, 43Sidney PlofskyIda Plofsky, 88Michelle Mcewen, 51Nathan Plofsky, 58
Connected to:
Philip C Plofsky, 65Cheryl L Plog, 65Corey M Plog, 40David Plog, 41Jonathan Plog, 31Laura S Plog, 52Mildred F Plog, 96Tyler J Plog, 52Kenneth M Ploger, 59Linda S Plogger, 68

Jordan Plofsky Phones & Addresses

  • 415 North Water St APT 2506, Chicago, IL 60611 (312) 854-3803
  • San Jose, CA
  • San Luis Obispo, CA
  • Los Angeles, CA
  • Sunnyvale, CA
  • Carlsbad, CA

Work

Company: Altera Feb 2001 to Sep 2012 Position: Senior vice president - various responsibilites

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: University of Illinois at Urbana - Champaign 1978 to 1982 Specialities: Electrical Engineering

Skills

Ic • Semiconductors • Semiconductor Industry • Soc • Asic • Fpga • Eda • Electrical Engineering • Altera • Wireless • Digital Signal Processors • Verilog • Processors • Hardware Architecture • Cmos • Silicon • Integrated Circuit Design • Microprocessors

Languages

English

Interests

Economic Empowerment • Civil Rights and Social Action • Politics • Education • Science and Technology • Disaster and Humanitarian Relief

Industries

Semiconductors

Resumes

Resumes

Jordan Plofsky Photo 1

Jordan Plofsky

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Location:
415 North Water St, Chicago, IL 60611
Industry:
Semiconductors
Work:
Altera Feb 2001 - Sep 2012
Senior Vice President - Various Responsibilites
Lsi Corporation 1996 - 2001
Vpgm Networking Division - Last Position
Analog Devices Nov 1989 - Sep 1996
Various
Harris Semiconductor 1983 - 1990
Various
Education:
University of Illinois at Urbana - Champaign 1978 - 1982
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Ic
Semiconductors
Semiconductor Industry
Soc
Asic
Fpga
Eda
Electrical Engineering
Altera
Wireless
Digital Signal Processors
Verilog
Processors
Hardware Architecture
Cmos
Silicon
Integrated Circuit Design
Microprocessors
Interests:
Economic Empowerment
Civil Rights and Social Action
Politics
Education
Science and Technology
Disaster and Humanitarian Relief
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jordan Plofsky
Senior Vice President, Marketing
Altera Corporation
Semiconductors and Related Devices
101 Innovation Dr, San Jose, CA 95134
Jordan Plofsky
Senior Vice President, Marketing
Altera Corporation
Semiconductors and Related Devices
101 Innovation Dr, San Jose, CA 95134
Jordan Plofsky
Manager
Analog Devices, Inc
Mfg Semiconductors/Related Devices · Semiconductor and Related Device Manufacturing
3550 N 1 St, San Jose, CA 95134
(408) 382-3280, (408) 383-9512, (408) 382-3000, (408) 727-9222
Jordan Plofsky
Managing
RESCUE PROPERTY SOLUTIONS, LLC
Nonresidential Building Operator
2781 Whistler St, Melbourne, FL 32904
2903 W New Hvn Ave 312, Melbourne, FL 32904
2903 W New Hvn Ave, Melbourne, FL 32904
415 E North Water St, Chicago, IL 60611
Jordan Plofsky
Senior Vice President, Marketing
Altera
Semiconductors · Mfg of Semiconductors and Related Devices · Mfg Semiconductors · Mfg Semiconductors and Related Devices · Mfg Semiconductors Software Development · Mfg Semiconductor Chips & Related Software · Semiconductor Devices (Manufac · Semiconductor and Related Device Manufacturing
101 Innovation Dr, San Jose, CA 95134
101 Innovation Dr Attn Tax, San Jose, CA 95134
Suite SUITE J, Phoenix, AZ 85021
131 Innovation Dr, San Jose, CA 95134
(408) 544-7000, (408) 544-7900, (408) 544-6410, (408) 428-0463

Publications

Us Patents

Dsp Design System Level Power Estimation

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US Patent:
7143368, Nov 28, 2006
Filed:
Jun 10, 2004
Appl. No.:
10/866391
Inventors:
Jordan Plofsky - Sunnyvale CA, US
Philippe Molson - San Jose CA, US
Francois Pequillat - Issy les Moulineaux, FR
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 1, 716 18
Abstract:
Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

Embedded Microprocessor For Integrated Circuit Testing And Debugging

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US Patent:
7539900, May 26, 2009
Filed:
Jul 29, 2003
Appl. No.:
10/629508
Inventors:
Jordan Plofsky - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 11/00
US Classification:
714 30
Abstract:
A technique for embedding a microprocessor into an integrated circuit allows on-chip testing and debugging. The microprocessor present on the chip tests and debugs the rest of the chip. Both testing and debugging of a programmable logic device use an embedded microprocessor. Testing is performed by the device manufacturer using a test system. Debugging is performed by a user using a host computer. A PLD includes programmable logic, an embedded microprocessor and separate memory. Testing or debugging routines, patterns, simulations, etc. , are downloaded onto the memory. The microprocessor executes the test or debug routine and uploads results to the test system or host computer. The technique is applicable any integrated circuit that can include an embedded microprocessor and associated memory, such as a PLD, an ASIC, a memory chip, or an analog chip.

Dsp Design System Level Power Estimation

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US Patent:
7882457, Feb 1, 2011
Filed:
Nov 15, 2006
Appl. No.:
11/600436
Inventors:
Jordan Plofsky - Sunnyvale CA, US
Philippe Molson - San Jose CA, US
Francois Pequillat - Issy les Moulineaux, FR
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 1, 716 18
Abstract:
Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

Dsp Design System Level Power Estimation

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US Patent:
8402419, Mar 19, 2013
Filed:
Jan 19, 2011
Appl. No.:
13/009467
Inventors:
Jordan Plofsky - Sunnyvale CA, US
Philippe Molson - San Jose CA, US
Francois Pequillat - Issy les Moulineaux, FR
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716132, 716101, 716126
Abstract:
Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

Systems Including An I/O Stack And Methods For Fabricating Such Systems

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US Patent:
20120228760, Sep 13, 2012
Filed:
Mar 11, 2011
Appl. No.:
13/046247
Inventors:
Chooi Pei Lim - Bayan Lepas, MY
Jordan Plofsky - San Jose CA, US
Yee Liang Tan - Gelugor, MY
Teik Tiong Toong - Simpang Ampat, MY
Assignee:
ALTERA CORPORATION - San Jose CA
International Classification:
H01L 23/48
H01L 21/50
US Classification:
257737, 438109, 257E21499, 257E2301
Abstract:
Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

Techniques For Providing Early Failure Warning Of A Programmable Circuit

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US Patent:
7062685, Jun 13, 2006
Filed:
Dec 11, 2002
Appl. No.:
10/317436
Inventors:
Jordan Plofsky - Sunnyvale CA, US
Jayabrata Ghosh Dastidar - Santa Clara CA, US
Michael Harms - Pleasanton CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 11/00
US Classification:
714 47
Abstract:
Techniques for monitoring the performance of a programmable circuit and to provide an early warning of a potential failure are provided. A processor monitors the performance of components on a programmable circuit over time. The processor stores performance characteristics for the components in memory. If the performance characteristics for particular components fall outside tolerance ranges, these components may to fail to operate according to specifications. Once the performance characteristics for particular components are outside the tolerance ranges, the processor sends out an alert signal. The alert signal indicates the possibility that the performance of the programmable circuit may violate the specifications in the future. The processor may repair the programmable circuit by re-routing around the problem components.
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Jordan S Plofsky from Chicago, IL, age ~63 Get Report