Kevin T Majerus

20210304805, Sep 30, 2021

Mar 26, 2020

16/831524

- Boise ID, US
Riccardo Pazzocco - Verona (VR), IT
Jonathan J. Strand - Boise ID, US
Kevin T. Majerus - Boise ID, US

G11C 11/22
G11C 29/50

Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

20210149573, May 20, 2021

Nov 15, 2019

16/686071

- Boise ID, US
Kevin T. Majerus - Boise ID, US

G06F 3/06
G11C 11/22

Methods, systems, and devices for quick activate for memory sensing are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a testing procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received activate command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received activate command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

20210134340, May 6, 2021

Nov 5, 2019

16/675065

- Boise ID, US
Kevin T. Majerus - Boise ID, US

G11C 11/22
G11C 29/08

Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

20200411132, Dec 31, 2020

Jun 26, 2019

16/453905

- Boise ID, US
TAMARA SCHMITZ - SCOTTS VALLEY CA, US
JONATHAN D. HARMS - MERIDIAN ID, US
JEREMY CHRITZ - SEATTLE WA, US
KEVIN MAJERUS - BOISE ID, US

MICRON TECHNOLOGY, INC. - Boise ID

G11C 29/00
G06F 3/06
G06F 12/02
G06F 12/126

Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.