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Kevin J Shuholm

from Grass Valley, CA
Age ~58
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Also known as:
Kevin M
Phone and address:
13956 Auburn Rd, Grass Valley, CA 95949
(530) 272-3639
Related to:
Clara F Maloney, 88Genny CarterJustin Carter, 42Kerri Burrow, 49Juliana Burrow, 78
Connected to:
Hong W Shuhong, 63Sun Shuhong, 32George X Shui, 65Sheung H Shui, 39Ezaki N Shuichi, 51Abbas Shuja, 31Najma Shuja, 68Ratibu Shujaa, 47Robert H Shujman, 46Bonnie Shuk, 82

Kevin Shuholm Phones & Addresses

  • 13956 Auburn Rd, Grass Valley, CA 95949 (530) 272-3639
  • Chico, CA

Work

Company: Miranda technologies Oct 1997 Position: Senior hw engineer ii

Education

Degree: BSEE School / High School: California State University-Chico 1984 to 1989 Specialities: Electrical/Electronic Engineering

Skills

Video • Fpga • Digital Video • Verilog • Analog • Broadcast • Product Development • Television • Engineering

Industries

Broadcast Media

Resumes

Resumes

Kevin Shuholm Photo 1

Staff Engineer

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Location:
13956 Auburn Rd, Grass Valley, CA 95949
Industry:
Broadcast Media
Work:
Miranda Technologies since Oct 1997
Senior HW Engineer II
GVG 1990 - 1997
Engineer
Thomson - Grass Valley 1990 - 1997
Engineer
Education:
California State University-Chico 1984 - 1989
BSEE, Electrical/Electronic Engineering
Skills:
Video
Fpga
Digital Video
Verilog
Analog
Broadcast
Product Development
Television
Engineering

Publications

Us Patents

Apparatus And Method For Extracting Data Values From A Signal Encoded With Aes3 Data

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US Patent:
6573759, Jun 3, 2003
Filed:
Jan 18, 2001
Appl. No.:
09/766014
Inventors:
Kevin J. Shuholm - Grass Valley CA
Assignee:
Nvision, Inc. - Grass Valley CA
International Classification:
H03K 908
US Classification:
327 33, 327 31
Abstract:
Apparatus for determining nominal pulse duration values in a signal encoded with an AES3 data stream includes a first circuit for measuring duration of each pulse of the signal and providing a sequence of duration values. A second circuit detects a maximum duration value, corresponding to duration of three bit cells, and provides first and second duration values corresponding to one bit cell and two bit cells respectively.

Circuit For Processing A Digital Data Signal

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US Patent:
6597731, Jul 22, 2003
Filed:
Mar 17, 2000
Appl. No.:
09/527975
Inventors:
Kevin J. Shuholm - Grass Valley CA
Assignee:
Nvision, Inc. - Grass Valley CA
International Classification:
H04B 138
US Classification:
375220, 375257
Abstract:
A circuit for processing a differential serial digital data signal provided by a signal source includes a transmission line and an amplifier. A first capacitor couples a first conductor of the transmission line to a first input of the amplifier and a second capacitor couples a second conductor of the transmission line to a second input of the amplifier, and a termination resistor is connected between the first and second inputs of the amplifier. The capacitance value of the first capacitor is such that the time constant of the first capacitor and the termination resistor is about one-third of one bit time of the serial digital data signal and the capacitance value of the second capacitor is substantially greater than the capacitance value of the first capacitor.

Expandable Router

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US Patent:
6680939, Jan 20, 2004
Filed:
Sep 14, 2000
Appl. No.:
09/661844
Inventors:
Donald S. Lydon - Grass Valley CA
Charles S. Meyer - Nevada City CA
Kevin J. Shuholm - Grass Valley CA
Jeffrey S. Evans - Grass Valley CA
Assignee:
NVision, INC - Grass Valley CA
International Classification:
H04L 1250
US Classification:
370366, 370386
Abstract:
A routing switch includes a first router module having N signal input terminals, M signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the N signal output terminals. The router further includes a second router module having N signal input terminals, M signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the M signal output terminals. The expansion output terminal of the first router module is connected to the expansion input terminal of the second router module and the expansion output terminal of the second router module is connected to the expansion input terminal of the first router module.

Audio/Video Router

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US Patent:
8359417, Jan 22, 2013
Filed:
Jan 6, 2011
Appl. No.:
12/986113
Inventors:
Kevin J. Shuholm - Grass Valley CA, US
Jeffrey S. Evans - Grass Valley CA, US
Robert W. Hudelson - Grass Valley CA, US
Charles S. Meyer - Nevada City CA, US
Assignee:
Miranda Technologies Inc. - Montreal
International Classification:
G06F 3/00
G06F 5/00
G06F 13/12
G06F 13/38
US Classification:
710 64, 710 1, 710 36, 710 51, 710 62, 710 65
Abstract:
A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.

Crosstalk Reduction Circuit For Crosspoint Matrix

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US Patent:
52870669, Feb 15, 1994
Filed:
May 15, 1992
Appl. No.:
7/883508
Inventors:
John E. Liron - Grass Valley CA
Grant T. McFetridge - Nevada City CA
Kevin J. Shuholm - Grass Valley CA
Assignee:
The Grass Valley Group - Nevada City CA
International Classification:
H03B 100
US Classification:
328163
Abstract:
A crosstalk reduction circuit compensates for input to output capacitance coupling of each switch of a crosspoint matrix and for output to common level capacitance coupling for each integrated circuit chip that makes up the crosspoint matrix. Each input signal to the crosspoint matrix is capacitively scaled, summed and inverted to produce an "off" isolation compensation signal, and each output signal from the crosspoint matrix is capacitively scaled, summed and inverted to produce an output isolation compensation signal. Each compensation signal is resistively scaled for each output signal, and the scaled compensation signals are subtracted from the output signals to reduce the crosstalk in the output signals.

Digital Audio Frame And Block Synchonization

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US Patent:
58595490, Jan 12, 1999
Filed:
Jun 13, 1997
Appl. No.:
8/874527
Inventors:
Kevin J. Shuholm - Grass Valley CA
Assignee:
Tektronix, Inc. - Wilsonville OR
International Classification:
H03L 706
US Classification:
327151
Abstract:
A digital audio frame and block synchronization signal is generated from a reference clock having a nominal 50% duty cycle except that one out of every N cycles has a different duty cycle, where N corresponds to a block span of ancillary data within the frame samples of the digital audio. A phase locked loop includes a loop counter that provides a sample clock synchronized with the reference clock. A block counter subdivides the sample clock by N to produce a block clock. A logic circuit has the reference clock and a current count from the loop counter as inputs, and detects when the Nth non-50% duty cycle occurs to generate a reset signal. The reset signal is used to reset the block counter so that the block clock is synchronized with the reference clock.

Digital Audio Receiver With Multi-Channel Swapping

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US Patent:
61049972, Aug 15, 2000
Filed:
Apr 22, 1998
Appl. No.:
9/064805
Inventors:
Kevin J. Shuholm - Grass Valley CA
Assignee:
Grass Valley Group - Nevada City CA
International Classification:
H04K 110
US Classification:
704500
Abstract:
A digital audio receiver with multi-channel swapping capabilities receives as inputs at least two AES serial digital audio streams. The audio streams are decoded, and each audio channel is stored in a separate buffer. The outputs of the buffers are input to at least two selectors. The selectors under user control select for each output digital audio stream which channels are represented. The recombined digital audio streams are then input to a conventional router cross-point matrix for directing to a desired destination and formatted into new AES serial digital audio streams.

System Of Switching Video Of Two Different Standards

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US Patent:
59055383, May 18, 1999
Filed:
Oct 15, 1997
Appl. No.:
8/951190
Inventors:
Kevin J. Shuholm - Grass Valley CA
John D. Boote - Nevada City CA
Iz V. Olmez - Grass Valley CA
Assignee:
Tektronix, Inc. - Wilsonville OR
International Classification:
H04N5/46
US Classification:
348555
Abstract:
A system for switching video of two different standards that uses a single crosspoint matrix and a single local controller coupled to two memory blocks for storage of crosspoint selection data. The crosspoint selection data is written to the crosspoint matrix according to the video reference signals that correspond to the crosspoint selection data to be written. Switching of the crosspoints then occurs according to the video reference signal corresponding to the crosspoints to be switched.
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Kevin J Shuholm from Grass Valley, CA, age ~58 Get Report