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Koichi E Nomura

from Gilbert, AZ
Age ~54

Koichi Nomura Phones & Addresses

  • Gilbert, AZ
  • Cornville, AZ
  • 3238 Glenrosa Ave, Phoenix, AZ 85017 (602) 544-0416
  • Scottsdale, AZ
  • Maricopa, AZ
  • 1887 E Pinto Dr, Gilbert, AZ 85296

Education

Degree: High school graduate or higher

Publications

Us Patents

Clock Circuit With Clock Transfer Capability And Method

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US Patent:
8204166, Jun 19, 2012
Filed:
Oct 8, 2007
Appl. No.:
11/868711
Inventors:
Srinivasa R. Bommareddy - Gilbert AZ, US
Uday Padmanabhan - Chandler AZ, US
Samir J. Soni - Chandler AZ, US
Koichi E. Nomura - Gilbert AZ, US
Nicholas F. Jungels - Gilbert AZ, US
Vivek Bhan - Chandler AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03L 7/06
H04Q 1/20
US Classification:
375354, 375371, 375373, 375226, 375294, 327 2, 327147, 327144
Abstract:
An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Timing Method And Apparatus For Interleaving Pio And Dma Data Transfers

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US Patent:
57940720, Aug 11, 1998
Filed:
May 23, 1996
Appl. No.:
8/652780
Inventors:
Koichi Eugene Nomura - Phoenix AZ
Gary D. Hicok - Mesa AZ
David K. Cassetti - Tempe AZ
Franklyn H. Story - Chandler AZ
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06F 1700
US Classification:
395860
Abstract:
The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is operatively connected to a plurality of storage mediums, a main memory and a central processing unit (CPU). The controller interface is preferably configured to receive and detect data transfer protocol requests having different timing parameters. Once the controller interface receives a data transfer protocol request, an arbitration unit that is operatively coupled to said controller interface assigns priorities to the detected data transfer protocols having different timing parameters. The arbitration unit then compares the assigned priorities, and interrupts an on-going data transfer protocol when a newly received data transfer protocol is assigned a higher priority. The data transfer protocol assigned the high priority is then commenced and proceeds to completion. Once the high priority data transfer protocol is complete, the interrupted data transfer protocols may be resumed.

Selecting A Test Data Input Bus To Supply Test Data To Logical Blocks Within An Integrated Circuit

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US Patent:
59369760, Aug 10, 1999
Filed:
Jul 25, 1997
Appl. No.:
8/910590
Inventors:
Franklyn H. Story - Chandler AZ
Koichi Eugene Nomura - Phoenix AZ
Michael James Fickes - Tempe AZ
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G01R 3128
G06F 1100
US Classification:
371 221
Abstract:
A testing apparatus and method are for testing a plurality of logic blocks within an integrated circuit. The integrated circuit includes a test data input bus, a test data output bus coupled to the output of each logic block, and test enable means which includes selection means coupled between the plurality of logic blocks and the test data input bus. The test enable means selects a first logic block from the plurality of logic blocks, and the selection means selectively inputs to each logic block either normal operating input or the test data. The test results are received from the first logic block through the test data output bus.
Koichi E Nomura from Gilbert, AZ, age ~54 Get Report