Search

Kota Takamatsu Phones & Addresses

  • Cupertino, CA

Work

Company: Intersil Jun 2012 Address: Milpitas Position: Asic design engineer lead

Education

Degree: BSEE School / High School: Waseda University 1993 to 1999 Specialities: Supersemconductor

Skills

Asic • Soc • Digital Signal Processors • Static Timing Analysis • Dft • Logic Synthesis • Fpga • Formal Verification • Atpg • Specman • Pipelines • Ddr2 Design • Mbist • Cache Design • Mmu • Digital Filters • Digital Pll

Languages

Japanese • English

Interests

Bicycle • Running • Motorcycle • Ski and Kayak Fishing

Industries

Semiconductors

Resumes

Resumes

Kota Takamatsu Photo 1

Principal Ic Design Engineer

View page
Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Intersil - Milpitas since Jun 2012
ASIC Design Engineer Lead

Intersil - Milpitas, CA May 2010 - Jun 2012
Design Engineer Lead

Techwell - San Jose, CA May 2009 - May 2010
ASIC Design Engineer

Techwell Japan - Tokyo, Japan Aug 2007 - May 2009
Senior LSI Design Engineer

Sony - Atsugi, Kanagawa, Japan Oct 2003 - Aug 2007
Project Manager, SoC Design Lead
Education:
Waseda University 1993 - 1999
BSEE, Supersemconductor
Skills:
Asic
Soc
Digital Signal Processors
Static Timing Analysis
Dft
Logic Synthesis
Fpga
Formal Verification
Atpg
Specman
Pipelines
Ddr2 Design
Mbist
Cache Design
Mmu
Digital Filters
Digital Pll
Interests:
Bicycle
Running
Motorcycle
Ski and Kayak Fishing
Languages:
Japanese
English
Kota S Takamatsu from Cupertino, CA, age ~50 Get Report