US Patent:
20150205726, Jul 23, 2015
Inventors:
- San Diego CA, US
Gheorghe Calin Cascaval - Palo Alto CA, US
Madhukar Nagaraja Kedlaya - Santa Clara CA, US
Dario Suarez Gracia - Santa Clara CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 12/08
G06F 9/38
G06F 9/30
Abstract:
Aspects include a computing devices, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.