Mathew Accapadi

7464237, Dec 9, 2008

Oct 27, 2005

11/259898

Jos M. Accapadi - Austin TX, US
Mathew Accapadi - Austin TX, US
Andrew Dunshea - Austin TX, US
Dirk Michel - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711162, 711112, 711161, 202204, 202205

A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e. g. , processing unit, peripheral, etc. ) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive.

7487503, Feb 3, 2009

Aug 12, 2004

10/916976

Jos Manuel Accapadi - Austin TX, US
Mathew Accapadi - Austin TX, US
Andrew Dunshea - Austin TX, US
Mark Elliott Hack - Cedar Park TX, US
Agustin Mena, III - Austin TX, US
Mysore Sathyanarayana Srinivas - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46
G06F 13/24

718103, 710262

Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.

7543124, Jun 2, 2009

Jul 9, 2008

12/170218

Mathew Accapadi - Austin TX, US
Dirk Michel - Austin TX, US
Andrew Dunshea - Austin TX, US
Jos M. Accapadi - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 12/07
G06F 12/57

711159, 711133

A computer-implemented system, method, and program product is disclosed for managing memory pages in a memory that includes a page replacement function. The method includes detecting that a sequence of pages is read by an application into the memory. The method continues by initiating a read-ahead to access a plurality of pages including the sequence of pages and a next page that has not yet been read, and storing the plurality in a page frame table of the memory. During the read-ahead, the method sets a soft-pin bit in the page frame table corresponding to each of the pages of the plurality of pages in the read-ahead. Each the soft-pin bit temporarily reserves its respective page from replacement by the page replacement function.

7861051, Dec 28, 2010

Jun 20, 2008

12/143552

Jos M. Accapadi - Austin TX, US
Mathew Accapadi - Austin TX, US
Andrew Dunshea - Austin TX, US
Dirk Michel - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711162, 711112

A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e. g. , processing unit, peripheral, etc. ) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive.

7962913, Jun 14, 2011

Dec 23, 2008

12/342352

Jos Manuel Accapadi - Austin TX, US
Mathew Accapadi - Austin TX, US
Andrew Dunshea - Austin TX, US
Mark Elliott Hack - Cedar Park TX, US
Agustin Mena, III - Austin TX, US
Mysore Sathyanarayana Srinivas - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46
G06F 13/24

718103, 718100, 718104, 710262

Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.

8037203, Oct 11, 2011

Feb 19, 2004

10/782668

Jos Manuel Accapadi - Austin TX, US
Mathew Accapadi - Austin TX, US
William Lee Britton - Austin TX, US
Andrew Dunshea - Austin TX, US
Dirk Michel - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 15/173

709238, 709223, 709228, 709230, 707705, 398106

Methods, systems, and products are disclosed for user defined preferred DNS routing that include mapping for a user in a data communications application a domain name of a network host to a network address for a preferred DNS server, wherein the preferred DNS server has a network address for the domain name; receiving from the user a request for access to a resource accessible through the network host; and routing to the preferred DNS server a DNS request for the network address of the network host, the DNS request including the domain name of the network host. In typical embodiments, mapping a domain name to a network address for a preferred DNS server is carried out by storing, through the data communication application, the domain name in association with the network address for a preferred DNS server in a data structure in computer memory.

8307188, Nov 6, 2012

Nov 10, 2009

12/615673

Mathew Accapadi - Austin TX, US
Dirk Michel - Austin TX, US
Bret Ronald Olszewski - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 12/02

711173, 711170

An information handling system (IHS) loads an application that may include startup code and steady state operation code. The IHS allocates one region of system memory to the startup code and another region of system memory to the steady state operation code. A programmer inserts a memory release call command at a location that marks the end of execution of the startup code. After executing the startup code, the operation system receives the memory release call command. In response to the memory release call command, the operating system releases or de-allocates the region of memory to which the IHS previously assigned to the startup code. This enables the released memory for use by code other than the startup code, such as other code pages, library pages and other code.

8327176, Dec 4, 2012

Mar 31, 2010

12/751227

Mathew Accapadi - Austin TX, US
Dirk Michel - Austin TX, US
Bret Ronald Olszewski - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 1/32

713323, 713300, 713320

Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases.