Michael K Ciraula

6873184, Mar 29, 2005

Sep 3, 2003

10/653802

Brian D. McMinn - Buda TX, US
Michael K. Ciraula - Round Rock TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F012/00

326 46, 710 52

An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.

7080170, Jul 18, 2006

Sep 3, 2003

10/653750

Brian D. McMinn - Buda TX, US
Michael K. Ciraula - Round Rock TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 3/00
G06F 9/30

710 52, 710 55, 712214, 712216

An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be written to at least a first entry, the control circuit is configured to generate a first age vector. The first age vector corresponds to the first entry, and is indicative of which of the plurality of entries contain data that is older than the data being written to the first entry. The control circuit is configured to select an entry for reading responsive to the plurality of age vectors. The selected entry has an attribute used to select the selected entry, and other entries indicated as storing older data in the age vector corresponding to the selected entry do not have the attribute.

7355881, Apr 8, 2008

Nov 22, 2005

11/285670

Floyd L. Dankert - Austin TX, US
Victor F. Andrade - Austin TX, US
Randal L. Posey - Austin TX, US
Michael K. Ciraula - Round Rock TX, US
Alexander W. Schaefer - Austin TX, US
Jerry D. Moench - Austin TX, US
Soolin Kao Chrudimsky - Austin TX, US
Michael C. Braganza - Austin TX, US
Jan Michael Huber - Austin TX, US
Amy M. Novak - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 11/00
G11C 7/10
G11C 7/00

365156, 365154, 36518902, 365202

A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

7366032, Apr 29, 2008

Nov 21, 2005

11/284313

Jan-Michael Huber - Austin TX, US
Michael Ciraula - Round Rock TX, US
Jerry D. Moench - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 7/10

36518904, 36518903, 36518905, 36518908

A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality of history cells is coupled to receive data from the base cell through a second port.

7417449, Aug 26, 2008

Nov 15, 2005

11/274595

Randal L. Posey - Austin TX, US
Michael K. Ciraula - Round Rock TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 31/02

324763, 324759, 714733

A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory structure, for example, and an access controller including one or more clock sources. In various embodiments, the clock sources may include a ring oscillator and a pulse width generator. These clock sources may be programmable to provide a clock signal having a variety of frequencies for accessing the storage structure. In one embodiment, the frequencies provided by the access controller may be higher than a frequency that can be supplied to the wafer from ATE. In another embodiment, the pulse width generator may be programmable to provide a pulse train having a variety of duty cycles.

7268591, Sep 11, 2007

Nov 15, 2005

11/274876

Jan-Michael Huber - Austin TX, US
Michael K. Ciraula - Round Rock TX, US

Advanced Micro Devices , Inc. - Sunnyvale CA

G11C 8/00
G06F 12/00

326105, 36523006, 711220, 711211

A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.

60469307, Apr 4, 2000

Sep 1, 1998

9/144871

Michael Kevin Ciraula - Round Rock TX
George McNeil Lattimore - Austin TX
Terry Lee Leasure - Georgetown TX
Gus Wai-Yen Yeung - Austin TX

International Business Machines Corporation - Armonk NY

G11C 1100

365156

A column (10) of a memory array includes a plurality of memory cells (11, 12) each having first and second independent access ports (T1, T2) and a cross-coupled memory latch (20). The first access port (T1) of each memory cell (11, 12) connects a first node (21) of the latch (20) to a first bit line (14), while the second access port (T2) of each memory cell connects a second node (22) of the latch (20) to a second bit line (15). A clearing arrangement (T7) is connected to the second bit line (15) for selectively coupling the second bit line to ground. A write driver is connected to the first bit line (14) for writing data to the memory cells (11, 12) in the form of single-ended signals. A memory cell is placed in a preset condition by simultaneously coupling the second node (22) to the second bit line (15) through the second access port (T2) and coupling the second bit line to ground through the clearing arrangement (T7). Once in the preset condition, data may be written to the cell by coupling the first bit line (14) to the first node (21) through the first access port (T1) and driving data to the first bit line.

60852895, Jul 4, 2000

Jul 18, 1997

8/896475

Larry Edward Thatcher - Austin TX
John Beck - Austin TX
Michael Kevin Ciraula - Round Rock TX

International Business Machines Corporation - Armonk NY

G06F 1200

711118

An improved load data formatter and methods for improving load data formatting and for cache line data organization are disclosed. The load data formatter includes a data selection mechanism, the data selection mechanism receiving a data cache line of a predetermined organization, and the data selection mechanism further supporting adjacent word swapping in the cache line. The load data formatter further includes at least two word selectors coupled to an output of the data selection mechanism, the at least two word selectors forming a doubleword on a chosen word boundary of the cache line. In a further aspect, the predetermined organization of the cache line is provided by grouping each corresponding bit of each byte in a cache line of data together, and expanding the grouping with an organization formed by one bit from a same byte within each word. The at least two word selectors may comprise even and odd multiplexers, and the load data formatter may also include splice registers, coupled to an output of one of the at least two selectors, which provide formatting of unaligned load access across a cache line boundary.