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Michael G Khazhinsky

from Austin, TX
Age ~53
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Also known as:
Michael Gregory Khazhinsky, Michael G Khazinsky, Mich Khazhinsky, Michael Y
Phone and address:
11209 Brista Way, Austin, TX 78726
(512) 219-0800
Related to:
Vadim G KhazhinskyEkaterina A KhazhinskyVadim G Khazhinsky, 49Susanna B Khazhinsky, 44
Connected to:
Mojahida Khazi, 38Tasrih Khazina, 65Mohamedaouf Khaznadar, 67Carol E Khaznehkatbi, 43Josephine M Khazraee, 65Davoud Khazraie, 69Valeriy Khazron, 70Marut Khdryan, 61Thor Kheam, 90Kimhak Kheang, 44

Michael Khazhinsky Phones & Addresses

  • 11209 Brista Way, Austin, TX 78726 (512) 219-0800
  • 2503 Aztec Dr, Austin, TX 78703 (512) 387-9804
  • 10610 Morado Cir, Austin, TX 78759
  • 12330 Metric Blvd, Austin, TX 78758 (512) 346-1714 (512) 973-9613
  • Silverthorne, CO
  • Kalamazoo, MI
  • Wilmette, IL
  • Tempe, AZ
  • Chandler, AZ
  • 11209 Brista Way, Austin, TX 78726 (512) 656-2814

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

m***[email protected]

Public records

Vehicle Records

Michael Khazhinsky

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Address:
11209 Brista Way, Austin, TX 78726
VIN:
JTJBC1BA7A2020843
Make:
LEXUS
Model:
RX 450H
Year:
2010

Resumes

Resumes

Michael Khazhinsky Photo 1

Board Of Directors

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Location:
2503 Aztec Dr, Austin, TX 78703
Industry:
Semiconductors
Work:
ESD Association since Sep 2011
Board of Directors
Silicon Laboratories since Nov 2010
Staff ESD Engineer/Designer
Freescale Semiconductor Mar 2004 - Nov 2010
ESD Team Lead/Engineer/Designer, Senior Member of Technical Staff
Motorola Semiconductor May 1997 - Mar 2004
Technology/Device/Circuit Simulation Engineer
Western Michigan University Aug 1993 - Apr 1997
Research Assistant, Research Fellow
Education:
Western Michigan University 1993 - 1997
Ph.D., Physics Moscow Institute of Electronic Technology (Technical University) (MIET) 1987 - 1993
M.S., Electrical Engineering, Physics
Skills:
Simulations
Semiconductors
Eda
Soc
Esd Control
Ic
Semiconductor Industry
Characterization
Debugging
Cmos
Rf
Physics
Asic
Mixed Signal
Electronics
Circuit Design
Analog Circuit Design
Microelectronics
Analog
System on A Chip
Failure Analysis
Engineering
Cadence Virtuoso
Modeling
Integrated Circuit Design
Automation
Physical Design
Languages:
English
Russian
Michael Khazhinsky Photo 2

Board Of Directors

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Location:
Austin, TX
Work:
Esd Association
Board of Directors

Publications

Us Patents

Method For Forming A Well Under Isolation And Structure Thereof

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US Patent:
6500723, Dec 31, 2002
Filed:
Oct 5, 2001
Appl. No.:
09/972397
Inventors:
Michael G. Khazhinsky - Austin TX
Aykut Dengi - Tempe AZ
James W. Miller - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2120
US Classification:
438382, 438298, 438383, 438450, 438526, 438530, 438947
Abstract:
A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

Electrostatic Discharge Circuit And Method Therefor

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US Patent:
6879476, Apr 12, 2005
Filed:
Jan 22, 2003
Appl. No.:
10/348814
Inventors:
Michael G. Khazhinsky - Austin TX, US
James W. Miller - Austin TX, US
Michael Stockinger - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H02H009/00
US Classification:
361 56
Abstract:
An ESD protection circuit () and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor () is to maximize the Vtof the N-channel transistor (). Vtis the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor () first occurs. In some embodiments, the ESD protection circuit () includes a diode () which provides an additional current path from the I/O pad to a first power supply node ().

Electrostatic Discharge Circuit And Method Therefor

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US Patent:
6900970, May 31, 2005
Filed:
Jan 22, 2003
Appl. No.:
10/348939
Inventors:
James W. Miller - Austin TX, US
Michael G. Khazhinsky - Austin TX, US
Michael Stockinger - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H02H009/04
US Classification:
361 56
Abstract:
An ESD protection circuit () and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor () is to maximize the Vt1 of the N-channel transistor (). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor () first occurs. In some embodiments, the ESD protection circuit () includes a diode () which provides an additional current path from the I/O pad to a first power supply node ().

Vertical Diode Formation In Soi Application

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US Patent:
7186596, Mar 6, 2007
Filed:
Jun 21, 2005
Appl. No.:
11/158022
Inventors:
Byoung W. Min - Austin TX, US
Laegu Kang - Austin TX, US
Michael Khazhinsky - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 29/72
US Classification:
438149, 438311, 257347, 257368, 257173
Abstract:
A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (), a first semiconductor layer (), and a first dielectric layer () disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first dielectric layer which exposes a portion of the substrate; (c) forming a first doped region () in the exposed portion of the substrate; and (d) forming anode () and cathode () regions in the first implant region.

Electrostatic Discharge Circuit And Method Therefor

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US Patent:
7236339, Jun 26, 2007
Filed:
Apr 21, 2005
Appl. No.:
11/111528
Inventors:
James W. Miller - Austin TX, US
Michael G. Khazhinsky - Austin TX, US
Michael Stockinger - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
An ESD protection circuit () and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor () is to maximize the Vt1 of the N-channel transistor (). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor () first occurs. In some embodiments, the ESD protection circuit () includes a diode () which provides an additional current path from the I/O pad to a first power supply node ().

Integrated Circuit With Multiple Independent Gate Field Effect Transistor (Migfet) Rail Clamp Circuit

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US Patent:
7301741, Nov 27, 2007
Filed:
May 17, 2005
Appl. No.:
11/130873
Inventors:
Michael G. Khazhinsky - Austin TX, US
Leo Mathew - Austin TX, US
International Classification:
H02H 3/22
US Classification:
361 56, 361111
Abstract:
A rail clamp circuit () includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (), and an ESD event detector circuit (). The MIGFET () has a source/drain path coupled between the first () and second () power supply voltage rails, and first and second gates. The ESD event detector circuit () is coupled between the first () and second () power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first () and second () power supply voltage rails, the ESD event detector circuit () provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET () while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET () conductive with relatively high conductivity.

Electronic Device And A Process For Forming The Electronic Device

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US Patent:
7432122, Oct 7, 2008
Filed:
Jan 6, 2006
Appl. No.:
11/327686
Inventors:
Leo Mathew - Austin TX, US
Michael G. Khazhinsky - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/00
H01L 21/84
H01L 21/20
H01L 21/36
US Classification:
438 48, 438149, 438479, 438480
Abstract:
An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

I/O Cell Esd System

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US Patent:
7446990, Nov 4, 2008
Filed:
Feb 11, 2005
Appl. No.:
11/056617
Inventors:
James W. Miller - Austin TX, US
Michael G. Khazhinsky - Austin TX, US
Michael Stockinger - Austin TX, US
James C. Weldon - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.
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Michael G Khazhinsky from Austin, TX, age ~53 Get Report