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Nathan N Geryk

from Queen Creek, AZ
Age ~54
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Also known as:
Nathan R Geryk
Phone and address:
34083 N Paseo Grande Dr, Queen Creek, AZ 85142
(480) 988-7373
Related to:
Alfred F HebertSuzanne Wozniak, 42Josephine MccraryAdam Wozniak, 44Melanie B Mancill, 62David Wozniak, 77
Connected to:
Micheal E Geryk, 69Andrea Gerytch, 47Alfred G Gerz, 89Anna Gerzan, 87Ignacio Gerze, 56Jessica L Gerze, 39Barica Gerzelj, 96Rodger H Gerzema, 81Gerald C Gerzeski, 57Fikret Gerzic, 68

Nathan Geryk Phones & Addresses

  • 34083 N Paseo Grande Dr, Queen Creek, AZ 85142 (480) 988-7373
  • 2680 E La Costa Dr, Chandler, AZ 85249
  • 4291 Kerby Way, Chandler, AZ 85249
  • Casa Grande, AZ
  • Rio Rancho, NM
  • Tempe, AZ
  • Gilbert, AZ
  • Maricopa, AZ

Work

Company: Marvell 2006 Position: Design engineer

Education

Degree: MSEE School / High School: The University of New Mexico 1993 to 1995

Skills

Low Power Design • Timing Closure • Logic Synthesis • Static Timing Analysis • Dft • Formal Verification • Floorplanning • Asic • Tcl • Systemverilog • Soc • Perl • Rtl Design • Physical Design • Semiconductors • Debugging • Verilog • Physical Verification • Vlsi • Starbucks Chauffeur • Microprocessors • Uvm • Arm

Industries

Semiconductors

Resumes

Resumes

Nathan Geryk Photo 1

Engineer, Physical Implementation

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Marvell since 2006
Design Engineer
Marvell Semiconductor since 2006
Design Engineer
Intel Corp 1995 - 2006
Design Engineer
Philips Semiconductor Dec 1993 - May 1995
Engineering Intern
Education:
The University of New Mexico 1993 - 1995
MSEE University of Rochester 1988 - 1993
BSEE Williston-Northampton 1984 - 1988
Skills:
Low Power Design
Timing Closure
Logic Synthesis
Static Timing Analysis
Dft
Formal Verification
Floorplanning
Asic
Tcl
Systemverilog
Soc
Perl
Rtl Design
Physical Design
Semiconductors
Debugging
Verilog
Physical Verification
Vlsi
Starbucks Chauffeur
Microprocessors
Uvm
Arm

Publications

Us Patents

Method Of Forming A Via Overlap

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US Patent:
6446873, Sep 10, 2002
Filed:
Oct 20, 2000
Appl. No.:
09/693533
Inventors:
Nathan Geryk - Gilbert AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06K 1900
US Classification:
235487, 438258, 257767, 257382, 257774, 257296, 357234
Abstract:
Briefly, in accordance with one embodiment of the invention, a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides. Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides. Briefly, in accordance with still another embodiment of the invention, an integrated cicuit includes: a semiconductor substrate, the semiconductor substrate having formed thereon an interconnect. The interconnect including at least two vias, the at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.

Method Of Forming A Via Overlap

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US Patent:
61664413, Dec 26, 2000
Filed:
Nov 12, 1998
Appl. No.:
9/191462
Inventors:
Nathan Geryk - Gilbert AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2348
H01L 2352
H01L 2940
US Classification:
257773
Abstract:
Briefly, in accordance with one embodiment of the invention a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides. Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides. Briefly, in accordance with still another embodiment of the invention, an integrated cicuit includes: a semiconductor substrate, the semiconductor substrate having formed thereon an interconnect. The interconnect including at least two vias, the at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.
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Nathan N Geryk from Queen Creek, AZ, age ~54 Get Report