Resumes
Resumes
Nenad Miladinovic Phones & Addresses
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Los Gatos, CA
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Honolulu, HI
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816 Laura Ct, Campbell, CA 95008
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Santa Clara, CA
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Mukilteo, WA
Publications
Us Patents
Methods And Apparatus For Computing A Probability Value Of A Received Value In Communication Or Storage Systems
View pageUS Patent:
8429500, Apr 23, 2013
Filed:
Mar 31, 2010
Appl. No.:
12/751960
Inventors:
Erich F. Haratsch - Bethlehem PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11C 29/00
US Classification:
714773, 714709
Abstract:
Methods and apparatus are provided for computing a probability value of a received value in communication or storage systems. A probability value for a received value in a communication system or a memory device is computed by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the probability value using the set of parameters associated with the identified segment. A probability value for a received value in a communication system or a memory device can also be computed by calculating the probability value for the received value using a first distribution, wherein the first distribution is predefined and wherein a mapped version of the first distribution approximates a distribution of the received values and wherein the calculating step is implemented by a processor, a controller, a read channel, a signal processing unit or a decoder.
Methods And Apparatus For Read-Side Intercell Interference Mitigation In Flash Memories
View pageUS Patent:
8462549, Jun 11, 2013
Filed:
Jun 30, 2009
Appl. No.:
13/001278
Inventors:
Erich F. Haratsch - Bethlehem PA, US
Milos Ivkovic - Allentown PA, US
Victor Krachkovsky - Allentown PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Johnson Yen - Fremont CA, US
Milos Ivkovic - Allentown PA, US
Victor Krachkovsky - Allentown PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Johnson Yen - Fremont CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11C 11/34
US Classification:
36518503, 36518512, 36518517, 36518518, 36518524, 36518533
Abstract:
Methods and apparatus are provided for read-side intercell interference mitigation in flash memories. A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.
Methods And Apparatus For Approximating A Probability Density Function Or Distribution For A Received Value In Communication Or Storage Systems
View pageUS Patent:
8504885, Aug 6, 2013
Filed:
Mar 31, 2010
Appl. No.:
12/751973
Inventors:
Erich F. Haratsch - Bethlehem PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G06F 11/00
US Classification:
714722, 714763
Abstract:
Methods and apparatus are provided for approximating a probability density function or distribution for a received value in communication or storage systems. A target distribution is approximated for a received value in one or more of a communication system and a memory device, by substantially minimizing a squared error between the target distribution of the received values and a second distribution obtained by mapping a predefined distribution, such as a Gaussian distribution, through a mapping function, wherein the second distribution has an associated set of parameters. The mapping function can be, for example, a piecewise linear function. The second distribution has a plurality of segments and each of the segments has an associated set of parameters. The associated set of parameters can be used to compute probability values, soft data values or log likelihood ratios.
Methods And Apparatus For Write-Side Intercell Interference Mitigation In Flash Memories
View pageUS Patent:
8526230, Sep 3, 2013
Filed:
Jun 30, 2009
Appl. No.:
13/001286
Inventors:
Erich F. Haratsch - Bethlehem PA, US
Milos Ivkovic - Sunnyvale CA, US
Victor Krachkovsky - Allentown PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Johnson Yen - Fremont CA, US
Milos Ivkovic - Sunnyvale CA, US
Victor Krachkovsky - Allentown PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Johnson Yen - Fremont CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11C 16/04
US Classification:
36518502, 36518503, 36518528, 36518533
Abstract:
Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
Methods And Apparatus For Synchronization Mark Detection Based On A Position Of An Extreme Distance Metric
View pageUS Patent:
8587888, Nov 19, 2013
Filed:
May 28, 2010
Appl. No.:
12/790249
Inventors:
Erich F. Haratsch - Bethlehem PA, US
Shaohua Yang - San Jose CA, US
Nenad Miladinovic - Campbell CA, US
Yuan Xing Lee - San Jose CA, US
Shaohua Yang - San Jose CA, US
Nenad Miladinovic - Campbell CA, US
Yuan Xing Lee - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11B 5/09
US Classification:
360 51
Abstract:
Methods and apparatus are provided for detection of a synchronization mark based on a position of an extreme distance metric. A synchronization mark is detected in a received signal by computing a distance metric between the received signal and an ideal version of the received signal expected when reading the synchronization mark, wherein the distance metric is computed for a plurality of positions within a search window; determining a substantially extreme distance metric within the search window; and detecting the synchronization mark based on a position of the substantially extreme distance metric. The distance metric can comprise a sum of square differences or a Euclidean distance between the received signal and the ideal version of the received signal.
Methods And Apparatus For Programming Multiple Program Values Per Signal Level In Flash Memories
View pageUS Patent:
8634250, Jan 21, 2014
Filed:
Jul 21, 2009
Appl. No.:
13/001295
Inventors:
Erich F. Haratsch - Bethlehem PA, US
Milos Ivkovic - Sunnyvale CA, US
Victor Krachkovsky - Allentown PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Johnson Yen - Fremont CA, US
Milos Ivkovic - Sunnyvale CA, US
Victor Krachkovsky - Allentown PA, US
Nenad Miladinovic - Campbell CA, US
Andrei Vityaev - San Jose CA, US
Johnson Yen - Fremont CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11C 11/34
US Classification:
36518522, 36518528, 36518519
Abstract:
Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.
Stochastic Stream Decoding Of Binary Ldpc Codes
View pageUS Patent:
8650451, Feb 11, 2014
Filed:
Jun 30, 2011
Appl. No.:
13/174537
Inventors:
Anantha Raman Krishnan - Tucson AZ, US
Nenad Miladinovic - Campbell CA, US
Yang Han - Sunnyvale CA, US
Shaohua Yang - Santa Clara CA, US
Nenad Miladinovic - Campbell CA, US
Yang Han - Sunnyvale CA, US
Shaohua Yang - Santa Clara CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03M 13/00
US Classification:
714752, 714758, 714801, 714760, 714755, 714746, 714751, 714780, 714800, 714804
Abstract:
Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.
Systems And Methods For Data Recovery
View pageUS Patent:
20110205653, Aug 25, 2011
Filed:
Feb 24, 2010
Appl. No.:
12/712136
Inventors:
George Mathew - San Jose CA, US
Shaohua Yang - Santa Clara CA, US
Haitao Xia - Mountain View CA, US
Nenad Miladinovic - Campbell CA, US
Shaohua Yang - Santa Clara CA, US
Haitao Xia - Mountain View CA, US
Nenad Miladinovic - Campbell CA, US
International Classification:
G11B 27/36
US Classification:
360 31, G9B 27052
Abstract:
Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is described that include a media defect detector and an anchor fixing circuit. The media defect detector is operable to identify a media defect, and the anchor fixing circuit is operable to identify a location relative to the media defect. The location is reproducible.