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Nikolaus M Klemmer

from Dallas, TX
Age ~58
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Also known as:
Nikolays Klemmer, Nikolau Klemmer, Nkolaus Klemmer, Nikolaus Klemme, Nikolaus Plemmer, Klemmer Nikolau, Nikolaus S
Phone and address:
6437 Danbury Ln, Dallas, TX 75214
Related to:
Lorraine S Edmunds, 77Richard L Edmunds, 50Richard L Edmunds, 80Margaret S Klemmer, 53
Connected to:
Evan A Klemmer, 57Gayle J Klemmer, 75Melissa L Klemmer, 44Peter P Klemmer, 67Roland N Klemmer, 92Viola M Klemmer, 101Beth C Klemoff, 75Hannah Klemola, 28Michelle T Klemola, 50Donna C Klemond, 90

Nikolaus Klemmer Phones & Addresses

  • 6437 Danbury Ln, Dallas, TX 75214
  • Apex, NC
  • Plano, TX
  • 214 Forest Brook Dr, Cary, NC 27511 (919) 303-0310
  • 102 Streamview Dr, Cary, NC 27511 (919) 303-0310
  • Durham, NC
  • Colton, TX

Work

Company: Texas instruments May 2010 Position: Rf ic design manager

Education

School / High School: Technische Universität Berlin 1992 to 1996

Skills

Design • Analog • Rf • Communications • Ic

Industries

Semiconductors

Resumes

Resumes

Nikolaus Klemmer Photo 1

Rf Ic Design Manager

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments since May 2010
RF IC Design Manager
ST-Ericsson, USA Feb 2009 - Dec 2009
RF IC Development Mgr.
Ericsson Mobile Platforms, USA Jul 2005 - Feb 2009
Analog/RF IC Design Manager
Analog Devices Mar 2004 - Jul 2005
Sr. Design Engineer
Ericsson Mobile Platforms, USA 2003 - 2004
Sr. Consulting Engineer
Education:
Technische Universität Berlin 1992 - 1996
Technische Universität München 1986 - 1992
Skills:
Design
Analog
Rf
Communications
Ic

Publications

Us Patents

Pll Loop Filter With Switched-Capacitor Resistor

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US Patent:
6259289, Jul 10, 2001
Filed:
Oct 1, 1999
Appl. No.:
9/410308
Inventors:
Nikolaus Klemmer - Apex NC
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H03L 706
US Classification:
327156
Abstract:
A phase-locked loop circuit having improved phase noise characteristics includes a voltage-controlled oscillator developing an oscillating output signal responsive to a voltage control input. A reference source provides a reference frequency signal. A phase detector is operatively connected to the voltage-controlled oscillator and the reference source developing an output proportional to a phase difference between the oscillating output signal and the reference frequency signal. A loop filter connects the phase detector output to the voltage control input. The loop filter includes a switched-capacitor equivalent resistor.

Ring Oscillator With Jitter Reset

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US Patent:
6337601, Jan 8, 2002
Filed:
Dec 8, 1999
Appl. No.:
09/457750
Inventors:
Nikolaus Klemmer - Apex NC
Assignee:
Ericsson Inc. - Rtp NC
International Classification:
H03B 502
US Classification:
331 34, 331 57, 331117 R, 331DIG 2
Abstract:
An improved low noise oscillator operates by periodically opening a ring oscillator to insert a reference input, thereby resetting any accumulated timing errors. The ring oscillator may be placed within the PLL to function as a voltage controlled oscillator. The loop in the ring oscillator is opened immediately prior to the arrival of the reference signal edge. While the ring oscillator loop is open, the reference signal is fed to the initial inverter instead of the initial inverter of the ring oscillator receiving the output from the last inverter of the ring oscillator. Shortly thereafter, the ring oscillator loop is closed again, and the structure operates as a conventional PLL with a ring oscillator until the next reset. The switching of the ring oscillator input is accomplished via a switch operable between a ring setting (loop back ring oscillator output) and a reset setting (reference signal as input). Switching the input as described restarts the ring oscillator with zero timing error and resets any previously accumulated timing error, thereby reducing phase noise.

Digitally Gain Controllable Amplifiers With Analog Gain Control Input, On-Chip Decoder And Programmable Gain Distribution

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US Patent:
6353364, Mar 5, 2002
Filed:
Dec 22, 1998
Appl. No.:
09/218389
Inventors:
Nikolaus Klemmer - Apex NC
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H03G 310
US Classification:
330279, 330282, 330129, 4552411
Abstract:
A digital gain controlled VGA is provided having a built-in decoder allowing for more standardized design of radio receivers by allowing a standardized gain control signal to be sent to the digital gain controlled VGA for controlling gain of the digital gain controlled VGA. Additionally, a digital gain controlled VGA is provided which is able to be controlled using an analog gain control signal. Use of the analog gain control signal allows the problems associated with the fast update rate required by the digital gain control word to be overcome. In addition, a digital gain controlled VGA is provided having a programmable decoder and noise and linearity circuit for changing the noise and linearity characteristics of the digital gain controlled VGA during operation.

One-Hot Decoded Phase Shift Prescaler

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US Patent:
6570946, May 27, 2003
Filed:
Nov 3, 1999
Appl. No.:
09/432623
Inventors:
David K. Homol - Apex NC
Nikolaus Klemmer - Apex NC
Al Jacoutot - Raleigh NC
Assignee:
Ericsson, Inc. - Research Triangle Park NC
International Classification:
H04L 2540
US Classification:
375371, 375373, 375375, 375376, 327113, 327151, 327152, 327153, 327160, 327162
Abstract:
A prescaler ( ) includes a first frequency divider ( ) configured to receive an input signal at an input frequency. The prescaler further includes a phase rotator ( ) coupled to the first frequency divider to produce a plurality of signal phases in response to the input signal. A frequency control circuit ( ) is configured as a one-hot decoder to select one signal phase of the plurality of signal phases. The one-hot decoder provides maximum speed of operation of the prescaler by eliminating decoding of the feedback signal.

Division Based Local Oscillator For Frequency Synthesis

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US Patent:
6708026, Mar 16, 2004
Filed:
Jan 11, 2000
Appl. No.:
09/481248
Inventors:
Nikolaus Klemmer - Apex NC
Antonio J. Montalvo - Raleigh NC
Steven L. White - Raleigh NC
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H04B 126
US Classification:
455314, 455131, 455205, 455260, 455313, 331 16
Abstract:
A programmable digital divider operates under the control of a division controller to derive a second synthesized frequency based on a first synthesized frequency. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division amount is an integer, but varies between integer values if necessary to achieve a non-integer average division value. The majority of the noise generated by the frequency synthesizer is generated away from the centerline frequency and is easily filtered by narrowband filter. The frequency synthesizer may optionally be incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for integration of the frequency synthesizer onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.

Integrated, Digitally-Controlled Crystal Oscillator

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US Patent:
6768389, Jul 27, 2004
Filed:
Sep 23, 2002
Appl. No.:
10/252198
Inventors:
Paul W. Dent - Pittsboro NC
Nikolaus Klemmer - Apex NC
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H03L 100
US Classification:
331175, 331177 R, 331158, 331116 R, 331 74
Abstract:
A quartz crystal oscillator comprises a balanced circuit with a quartz crystal resonator device connected in series resonance across a balanced, low-impedance node within a sustaining amplifier. A phase modulator such as a quadrature modulator is included in the feedback loop to allow programming of the loop phase shift thereby to alter the frequency point on the crystal resonance curve at which the circuit oscillates. The in-phase loop signal is hardlimited while the quadrature loop signal component is not hardlimited with the effect that the frequency control curve slope is more accurately defined. An active neutralization of the crystals parasitic shunt capacitance is disclosed for obtaining a linear frequency control curve.

Direct Automatic Frequency Control Method And Apparatus

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US Patent:
6856791, Feb 15, 2005
Filed:
Mar 14, 2002
Appl. No.:
10/097314
Inventors:
Nikolaus Klemmer - Apex NC, US
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H04B001/40
US Classification:
455 76, 455 42, 455260, 455113
Abstract:
An Automatic Frequency Control (AFC) circuit for a mobile terminal employs a fractional-N Phase Locked Loop (PLL) to directly reduce errors in the synthesized frequency, such as due to component tolerances, temperature drift, and the like. The frequency error is detected by the average speed of rotation of the I,Q constellation. A corresponding offset is added to the tuning frequency selection word prior to encoding, such as in a ΔΣ modulator, to generate an effective non-integer PLL frequency division factor over a specified duration. The ΔΣ modulator may include dithering the different integer values by a pseudo-random number to minimize noise in the output frequency spectrum introduced by the fractional-N division. Component and parameter selection allow a high degree of resolution in frequency control of the fractional-N PLL. By directly controlling for the frequency error, a DAC and XTAL oscillator tuning circuit may be eliminated from the AFC circuit.

Pll Cycle Slip Detection

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US Patent:
7003065, Feb 21, 2006
Filed:
Mar 9, 2001
Appl. No.:
09/803334
Inventors:
David Homol - Chandler AZ, US
Theron Jones - Apex NC, US
Nikolaus Klemmer - Apex NC, US
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H03D 3/24
US Classification:
375376, 375354, 375371, 375374, 331 10, 331 12, 331 16, 327 10, 327149
Abstract:
A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed 2π radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.
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Nikolaus M Klemmer from Dallas, TX, age ~58 Get Report