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Paul Werking Phones & Addresses

  • Phoenix, AZ
  • Grand Haven, MI
  • 26525 Table Meadow Rd, Auburn, CA 95602 (530) 269-1276
  • 4992 River Oaks Rd, Rockford, MN 55373 (763) 565-5368
  • 5835 Division Rd, Tipton, IN 46072 (765) 675-3782 (765) 675-5947
  • Pickerington, OH
  • Saginaw, MI
  • Novato, CA
  • Reynoldsburg, OH
  • Grass Valley, CA

Work

Company: Honeywell Apr 1, 2004 Position: Principal design engineer

Education

Degree: Masters School / High School: The Ohio State University 1994 Specialities: Electronics Engineering

Skills

Analog Ic Design

Languages

English

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Paul Werking Photo 1

Principal Design Engineer

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Location:
4992 River Oaks Rd, Rockford, MN 55373
Industry:
Electrical/Electronic Manufacturing
Work:
Honeywell
Principal Design Engineer
Education:
The Ohio State University 1994
Masters, Electronics Engineering
Purdue University 1975
Bachelors, Electronics Engineering
Indiana Wesleyan University 1971
Skills:
Analog Ic Design
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Paul Werking
Engineer
National Semiconductor Corporation
Engineering Services
488 Crown Pt Cir, Grass Valley, CA 95945
(530) 274-6554

Publications

Us Patents

Start Pulse Rejection For A Motor Commutation Pulse Detection Circuit

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US Patent:
6380757, Apr 30, 2002
Filed:
Jun 5, 2000
Appl. No.:
09/586802
Inventors:
Kenneth George Draves - Russiaville IN
Paul M. Werking - Tipton IN
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
G01R 3134
US Classification:
324772, 318254
Abstract:
Improved motor position detection circuitry based on commutation pulse counting, including a pulse recognition circuit, a pulse counting circuit, and a start pulse rejection circuit for rendering the position detection circuitry insensitive to start-up pulses associated with motor turn-on. The start pulse rejection circuit detects an off-to-on transition of a motor controller, and renders the position detection circuitry insensitive to start-up pulses generated in a predefined time window coinciding with the detected off-to-on transition. In a first mechanization, the start pulse rejection circuit maintains a nominal bias voltage at an input of the pulse recognition circuit for the duration of the predefined time window. In a second mechanization, the start pulse rejection circuit renders the pulse counting circuit insensitive to pulses produced by the pulse recognition circuit for the duration of the predefined time window.

Temperature Compensated Low Voltage Reference Circuit

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US Patent:
7122997, Oct 17, 2006
Filed:
Nov 4, 2005
Appl. No.:
11/267361
Inventors:
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
G05F 3/18
US Classification:
323313, 323316, 323907
Abstract:
A temperature compensated low voltage reference circuit can be realized with a reduced operating voltage overhead. This is accomplished in several ways including minimizing drain voltage variation at the drains of two inter-connected transistors and implementing a current conveyer in order to adjust the temperature coefficient of an output current or voltage. Various combinations of voltage minimization and temperature coefficient adjustments may be used to design a reference circuit to a circuit designer's preference. A temperature compensated current source may also be created. The temperature compensated current source may be used to provide a wide range of output voltages. All of the reference circuits may be constructed with various types of transistors including DTMOS transistors.

Methods And Systems For Comparing Currents Using Current Conveyor Circuitry

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US Patent:
7535264, May 19, 2009
Filed:
Aug 30, 2007
Appl. No.:
11/847973
Inventors:
James G. Hiller - Minnetonka MN, US
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H03K 5/22
US Classification:
327 66, 327 63, 327 65, 327 69, 327 70
Abstract:
Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output.

Torque Driving Circuit

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US Patent:
7552637, Jun 30, 2009
Filed:
Sep 19, 2006
Appl. No.:
11/533192
Inventors:
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
G01P 15/08
US Classification:
7351418
Abstract:
A torque driver that includes a regulator circuit for mitigating zero-g discontinuity effects and deadbanding is presented. An accelerometer may comprise the torque driver and the torque driver may be arranged to receive a control signal from a control circuit that is coupled to deflection sensing circuitry. When the accelerometer undergoes an acceleration the deflection sensing circuitry generates an acceleration signal that is communicated to the control circuit. The control circuit responsively generates a control signal, which the torque driver users to balance a proof mass beam within the accelerometer. The regulator circuit mitigates zero-g discontinuity effects and deadbanding by preventing the torque signal from producing torque signals that simultaneously track the control signal. To do this, the regulator circuit may include a rectifying buffer and/or a modulator.

Methods And Systems For Reducing A Sign-Bit Pulse At A Voltage Output Of A Sigma-Delta Digital-To-Analog Converter

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US Patent:
7619549, Nov 17, 2009
Filed:
Oct 18, 2007
Appl. No.:
11/874737
Inventors:
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H03M 3/00
US Classification:
341143, 341152
Abstract:
For a sigma-delta digital-to-analog converter (SD DAC) that includes a voltage output and a low-pass filter having a given order, methods and systems for reducing a sign-bit pulse at the voltage output of the SD DAC without requiring use of a higher order low-pass filter are disclosed. A method includes receiving a first waveform and a second waveform, the first and second waveforms having a first phase relationship; setting the first phase relationship between the first and second waveforms to a second phase relationship by aligning at least one of the first and second waveforms such that a transition of the second waveform is approximately half way between a rising edge and adjacent falling edge of the first waveform; upon setting the second phase relationship, multiplying the first and second waveforms to produce a digital input; and providing the digital input to the SD DAC.

Current Conveyor Based Instrumentation Amplifier

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US Patent:
7893759, Feb 22, 2011
Filed:
Mar 18, 2009
Appl. No.:
12/406424
Inventors:
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H03F 3/45
US Classification:
330 69
Abstract:
Current conveyor based instrumentation amplifiers are disclosed. Such instrumentation amplifiers may have the higher common mode rejection ratios (CMRR), lower area requirements in integrated circuits, fewer resistors, fewer resistor matching requirements, less noise, and less distortion than prior art instrumentation amplifiers. One embodiment, with two input voltage lines and one output voltage line, comprises a single current conveyor and two resistors. Another embodiment, with two input voltage lines and two output voltage lines, comprises two current conveyors and four resistors, possibly in two matched pairs. Buffers may be used for impedance, frequency, and phase delay adjustment on any or all of the voltage lines.

Differential Current-Mode Translator In A Sigma-Delta Digital-To-Analog Converter

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US Patent:
7903011, Mar 8, 2011
Filed:
Sep 12, 2007
Appl. No.:
11/898533
Inventors:
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H03M 1/66
US Classification:
341144, 323316, 327543
Abstract:
A differential current-mode sigma-delta digital-to-analog converter (SD DAC) and a method for generating positive and negative reference voltages in a sigma-delta digital analog converter are described. The SD DAC includes a low pass filter (LPF) having a first and second input. The SD DAC further includes a first resistance and a second resistance coupled together at a common node. The first resistance may be coupled to the first input of the LPF and the second resistance may be coupled to the second input of the LPF. Additionally, the SD DAC includes a current supply and a switching network for supplying current from the current supply to the first and second resistances. The current supply and the resistances operate to generate a first voltage and a second voltage at the first and second inputs of the LPF.

Current-Mode Sigma-Delta Digital-To-Analog Converter

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US Patent:
7956782, Jun 7, 2011
Filed:
Jun 11, 2009
Appl. No.:
12/456061
Inventors:
Paul M. Werking - Rockford MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H03M 3/00
US Classification:
341143, 341144
Abstract:
In general, this disclosure is directed to a differential current-mode sigma-delta digital-to-analog converter (SD DAC) with improved accuracy and reduced offset and gain errors. In one example, the SD DAC may include a current source configured to provide a differential current. The SD DAC may further include a switching network configured to adjust a polarity of the differential current according to a bit within the bit-stream to produce a differential current signal. The SD DAC may further include a current-to-voltage converter configured to convert the differential current signal to a differential voltage signal. In additional examples, the differential current source may include one or more source degeneration resistances. In further examples, the current-to-voltage converter may include a fully-differential operational amplifier. A low pass filter may be included within the current-to-voltage converter and/or coupled to the output of the current-to-voltage converter.
Paul M Werking from Phoenix, AZ, age ~72 Get Report