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Pieter J Woeltgens

from Yorktown Heights, NY
Age ~59
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Also known as:
Pieter Jm Woeltgens, Pieter M Woeltgens, Pieter J Woltgens, Pieter Jm Woltgens
Phone and address:
12 Moseman Rd, Yorktown Hgts, NY 10598
(914) 245-8096
Related to:
Ben Matthijs WoeltgensAnnemarie Jg Woltgens, 42Caronline S Woltgens, 63
Connected to:
Natalie R Woeltge, 46Glenn Woeltje, 105Karen Woempner, 49Karen A Woen, 79Anna G Woepke, 29Michelle M Woepke, 66Michele M Woeppel, 75Quinton J Woeppel, 54Karen M Woerdeman, 61Andrew J Woerheide, 37

Pieter Woeltgens Phones & Addresses

  • 12 Moseman Rd, Yorktown Heights, NY 10598 (914) 245-8096
  • Yorktown Hts, NY
  • 730 Fort Washington Ave, New York, NY 10040
  • Westchester, NY
  • Yorktown Hts, NY

Work

Company: Ibm Nov 1997 Position: Research staff member

Education

School / High School: Universiteit Utrecht 1983 to 1993

Industries

Computer Hardware

Resumes

Resumes

Pieter Woeltgens Photo 1

Phd At Ibm

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Position:
Research Staff Member at IBM, Research Staff Member at IBM Research, Research Staff Member at IBM T.J. Watson Research Center
Location:
Greater New York City Area
Industry:
Computer Hardware
Work:
IBM since Nov 1997
Research Staff Member
IBM Research since 1997
Research Staff Member
IBM T.J. Watson Research Center since 1997
Research Staff Member
Education:
Universiteit Utrecht 1983 - 1993

Publications

Us Patents

Physical Design System And Method

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US Patent:
8219943, Jul 10, 2012
Filed:
Apr 17, 2009
Appl. No.:
12/425603
Inventors:
John M Cohn - Richmond VT, US
James A. Culp - Downington PA, US
Ulrich A. Finkler - Mahopac NY, US
Mark A. Lavin - Katonah NY, US
Jin Fuw Lee - Yorktown Heights NY, US
Lars W. Liebmann - Poughquag NY, US
Gregory A. Northrop - Putnam Valley NY, US
Nakgeuon Seong - Wappingers Falls NY, US
Rama N. Singh - Bethel CT, US
Leon Stok - Croton on Hudson NY, US
Pieter J. Woeltgens - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 19/00
G03F 1/00
G21K 5/00
US Classification:
716 52, 716 53, 716 54, 716 55, 716111, 716106, 716132, 716136, 703 16, 700120, 700121, 700 98, 430 5, 378 35
Abstract:
A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Physical Design System And Method

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US Patent:
8473885, Jun 25, 2013
Filed:
Mar 7, 2012
Appl. No.:
13/413759
Inventors:
John M. Cohn - Richmond VT, US
James A. Culp - Downington PA, US
Ulrich A. Finkler - Mahopac NY, US
Mark A. Lavin - Katonah NY, US
Jin Fuw Lee - Yorktown Heights NY, US
Lars W. Liebmann - Poughquag NY, US
Gregory A. Northrop - Putnam Valley NY, US
Nakgeuon Seong - Wappingers Falls NY, US
Rama N. Singh - Bethel CT, US
Leon Stok - Croton on Hudson NY, US
Pieter J. Woeltgens - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716111, 716132, 716122, 716123, 716 52, 716 54, 716 55
Abstract:
A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Parameterized Semiconductor Chip Cells And Optimization Of The Same

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US Patent:
20080077889, Mar 27, 2008
Filed:
Sep 21, 2006
Appl. No.:
11/533814
Inventors:
Erwin Behnen - Austin TX, US
Gregory A. Northrop - Putnam Valley NY, US
James D. Warnock - Somers NY, US
Dieter Wendel - Schoenaich, DE
Pieter Joseph Woeltgens - Yorktown Heights NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 2
Abstract:
A method is provided for designing an integrated circuit utilizing an arrangement of at least one library cell having a plurality of parameterized input connection points disposed along a rod, a plurality of parameterized output connection points disposed along a wire and a cell structure to which the rod and wire are electrically connected; routing and making input and output connections to the library cells at the parameterized input connection points and the parameterized output connection points to satisfy design specifications of the integrated circuit. After determining which parameterized input connection points and parameterized output connection points are unused, the unused parameterized input connection points and parameterized output connection points are removed from each library cell of the integrated circuit design.

Independent Migration Of Hierarchical Designs With Methods Of Finding And Fixing Opens During Migration

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US Patent:
20080313581, Dec 18, 2008
Filed:
Jun 14, 2007
Appl. No.:
11/762832
Inventors:
Veit Gernhoefer - Holzgerlingen, DE
Matthew T. Guzowski - Essex Junction VT, US
Jason D. Hibbeler - Williston VT, US
Kevin W. McCullen - Essex Junction VT, US
Rani Narayan - San Jose CA, US
Stephen L. Runyon - Pflugerville TX, US
Leon J. Sigal - Monsey NY, US
Robert F. Walker - St. George VT, US
Pieter J. Woeltgens - Yorktown Heights NY, US
Xiaoyun K. Wu - Hopewell Junction NY, US
Xin Yuan - Williston VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 8
Abstract:
Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
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Pieter J Woeltgens from Yorktown Heights, NY, age ~59 Get Report