Praveen G Karandikar

7523265, Apr 21, 2009

Mar 18, 2005

11/083615

James Norris Dieffenderfer - Apex NC, US
Praveen G. Karandikar - Cary NC, US
Michael Bryan Mitchell - Fuquay-Varina NC, US
Thomas Philip Speier - Holly Springs NC, US
Paul Michael Steinmetz - Morrisville NC, US

International Business Machines Corporation - Armonk NY

G06F 12/00
G06F 13/00
G06F 13/28

711141, 711118, 711119, 711146

Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

7752396, Jul 6, 2010

Aug 22, 2008

12/196705

James Norris Dieffenderfer - Apex NC, US
Praveen G. Karandikar - Cary NC, US
Michael Bryan Mitchell - Fuquay-Varina NC, US
Thomas Philip Speier - Holly Springs NC, US
Paul Michael Steinmetz - Morrisville NC, US

International Business Machines Corporation - Armonk NY

G06F 12/00
G06F 13/00
G06F 13/28

711141

Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

20060279891, Dec 14, 2006

Jun 8, 2005

11/148090

James Dieffenderfer - Apex NC, US
Praveen Karandikar - Cary NC, US
Michael Mitchell - Fuquay-Varina NC, US
Thomas Speier - Holly Springs NC, US
Paul Steinmetz - Morrisville NC, US

International Business Machines Corporation - Armonk NY

H02H 5/04

361103000

A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.

20070038814, Feb 15, 2007

Aug 10, 2005

11/201221

James Dieffenderfer - Apex NC, US
Praveen Karandikar - Cary NC, US
Michael Mitchell - Fuquay-Varina NC, US
Thomas Speier - Holly Springs NC, US
Paul Steinmetz - Morrisville NC, US

International Business Machines Corporation - Armonk NY

G06F 13/28

711141000, 711146000

Embodiments include systems and methods for selectively inclusive multi-level cache. When data for which memory coherency is designated is received from a process and stored into a lower level cache the data is copied into a higher level of cache. When the data is snooped it is snooped from the higher level cache and not the lower level of cache. When data is invalidated in the higher level cache, the data is invalidated in the lower level cache also. Lines of higher level cache are inclusive of lower level cache lines for data for which memory coherency is designated, but need not be inclusive of data for which coherency is not designated.

20120159086, Jun 21, 2012

Dec 16, 2010

12/969644

Jason A. Cox - Raleigh NC, US
Praveen G. Karandikar - Cary NC, US
Eric F. Robinson - Raleigh NC, US
Mark J. Wolski - Apex NC, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G06F 12/08

711144, 711E12037

Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses.

20130184979, Jul 18, 2013

Jan 18, 2012

13/352521

Praveen Karandikar - Cary NC, US

International Business Machines Corporation - Armonk NY

G08G 1/16

701301

A method and system prevents accidental direction selection in a motor vehicle. The driver of the vehicle is alerted that the selected direction of the vehicle via the gear shift is opposite of the direction that the driver intends for the vehicle to move. The selected direction of the vehicle by the driver is initially detected. The invention then detects the driver's physical position and any objects in the immediate area surrounding the vehicle. Based on the information gathered from these detections, there is determination made regarding the vehicle direction selected by the driver. If the determination is the likelihood of an accident/collision if the vehicle moves in the selected direction, the present invention will alert the driver. In addition, an embodiment of the present invention may also include the ability to disable the vehicle in order to avoid a collision.