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Pushkar Mokashi Phones & Addresses

  • 6120 Meandering Creek Dr, Argyle, TX 76226 (940) 240-5201
  • 1734 Briaroaks Dr, Flower Mound, TX 75028 (972) 874-8573
  • Lewisville, TX
  • Louisville, KY
  • 1734 Briaroaks Dr, Flower Mound, TX 75028 (972) 816-4363

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Bachelor's degree or higher

Resumes

Resumes

Pushkar Mokashi Photo 1

Program Manager, Pmo

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Location:
6120 Meandering Creek Dr, Argyle, TX 76226
Industry:
Information Technology And Services
Work:
STMicroelectronics - Dallas/Fort Worth Area since Jun 2000
Program Manager

STMicroelectronics - Dallas/Fort Worth Area Jun 1996 - May 2000
Engineering Section Manager

STMicroelectronics - Dallas/Fort Worth Area Nov 1993 - Jun 1996
ASIC Design Engineer

IBM - IBM, Burlington Vermont Nov 1992 - Nov 1993
Associate Circuit Design Engineer
Education:
University of Louisville 1988 - 1990
MS, Electrical Engineering
Skills:
Asic
Semiconductors
Soc
Cmos
Program Management
Embedded Systems
System on A Chip
Embedded Software
Ic
Application Specific Integrated Circuits
Semiconductor Industry
R&D
Testing
Wireless
System Architecture
Processors
Integrated Circuits
Mixed Signal
Management
Eda
Set Top Box
Digital Signal Processors
Wireless Technologies
Analog
Digital Tv
Engineering Management
Product Engineering
Arm
Arm Architecture
Research and Development
Integrated Circuit Design
Dft
Team Management
Microelectronics
Rf
Project Management
Debugging
Electronics
Product Development
Cross Functional Team Leadership
Risk Management
People Management
Team Building
Certifications:
Scrum Alliance, License 000573437
Certified Scrum Master (Csm)
Project Management Professional
License 000573437
Pushkar Mokashi Photo 2

Pushkar Mokashi

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Pushkar Mokashi Photo 3

Pushkar Mokashi

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Publications

Us Patents

No Latency Pipeline

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US Patent:
55329705, Jul 2, 1996
Filed:
Mar 3, 1995
Appl. No.:
8/398334
Inventors:
Edward Butler - Richmond VT
Martin B. Lundberg - Milton VT
Pushkar U. Mokashi - Lewisville TX
Alfred L. Sartwell - Jericho VT
Hemen R. Shah - Essex Jct. VT
Robert Tamlyn - Jerico VT
International Classification:
G11C 800
US Classification:
36523005
Abstract:
An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n. sup. th bits of the SAM data.
Pushkar Upendra Mokashi from Argyle, TX, age ~56 Get Report