Rachid Kadri

8564946, Oct 22, 2013

Jan 8, 2009

13/139342

Rachid M. Kadri - Houston TX, US
John R. Grady - Cypress TX, US
David S. Blocker - Conroe TX, US
Wanda L. Bloomfield - Magnolia TX, US
George D. Megason - Spring TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1/16
H05K 13/00

36167937, 36167933, 295921

An electronic device includes a housing defining an enclosure, one or more processors in the enclosure, and one or more memory modules in the enclosure. Disk storage drives are provided in an in-line arrangement within the enclosure such that a rear portion of one disk storage drive is adjacent a front portion of another disk storage drive.

20020184174, Dec 5, 2002

May 1, 2001

09/846053

Rachid Kadri - Houston TX, US

G06F015/18
G06E001/00
G06G007/00

706/026000

A finite state electrical automaton modeled after a human neuron comprises a plurality of weighted inputs that pass into a state computing unit. A feedback mechanism changes the weights of the inputs as needed to control the response of the automaton to a desired output. A clock signal allows the automaton to function as a discrete time system. Unlike the threshold gates, the present automaton is capable of outputting an n-bit digital value analogous to a cell membrane potential. Because this automaton is capable of outputting more than two simple states it is a better building block for building neural nets.

20030074506, Apr 17, 2003

Oct 16, 2001

09/978512

Rachid Kadri - Houston TX, US
Lam Ngo - Raleigh NC, US
Pivithuru Perera - Raleigh NC, US
Mohamad Tawil - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F013/362

710/113000

A computer system extends the capacity of processors with limited external arbitration and operable only for two-way or dual mode operation. The two-way processors operate on a system bus in a four-way configuration at comparable performance levels to high end, four-way processors. A bus agent or arbiter allows the system to use two-way configured processors to operate with the performance of those specifically configured for four-way node operation.

20120175160, Jul 12, 2012

Apr 17, 2009

13/265323

Rachid M. Kadri - Houston TX, US
Stephen F. Contreras - Spring TX, US

H05K 1/16
H05K 3/30

174260, 29842

A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

20130151877, Jun 13, 2013

Oct 19, 2010

13/817852

Rachid M. Kadri - Houston TX, US
Reza M. Bacchus - Spring TX, US

G06F 1/32

713320

A computer power management system () can include power demand logic () of a computer component () that can generate a power demand signal corresponding to a predicted power demand determined for the computer component (). A voltage regulator down (VRD) system () includes at least one power phase (). The VRD system () can selectively adjust an input power to the computer component () based on power efficiency in response to the power demand signal.

20190028112, Jan 24, 2019

Jan 15, 2016

16/066800

- Houston TX, US
Rachid Kadri - Houston TX, US

H03M 1/12
G06F 1/04
G06F 13/16
G06F 12/0831

In one example, a mixed signaling socket includes a set of central processing unit (CPU) cores coupled via an inter-core link and a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core via a separate private bus. A field programmable gate array (FPGA) control circuit is coupled to the inter-core link and the set of analog circuits to provide predicable clock timing to the set of analog circuits and control signals to the set of CPU cores. An analog to digital module in at least one CPU core includes instructions to perform an analog to digital conversion to create a digital representation of the analog input using the predictable clock timing and control signals from the FPGA.

20160349834, Dec 1, 2016

Jan 30, 2014

15/114004

- Houston TX, US
Rachid M. KADRI - Houston TX, US

HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP - Houston TX

G06F 1/32
G06F 1/26

An example apparatus comprises a first compute node including a first processor; a second compute node including a second processor; an input/manta (I/O) interface to selectively couple the first and second compute nodes to a set of I/O resources; and a voltage regulator including a set of power phase circuits, the voltage regulator to operate in a fault tolerant mode to provide power from selected ones of a first portion of the set of power phase circuits to the first compute node and to provide power from selected ones of a second portion of the set of power phase circuits to the second compute node.

20150286544, Oct 8, 2015

Nov 29, 2012

14/435786

- Houston TX, US
Rachid M. Kadri - Houston TX, US

G06F 11/20

Examples disclose a multi-core circuit with a primary core associated with a primary portion of cache and a secondary core associated with a secondary portion of the cache. The secondary portion of the cache is redundant to the primary portion of the cache. Further, the examples of the multi-core circuit provide a control circuit to enable the secondary core for operation in response to a fault condition detected at the primary core, wherein the secondary portion of cache is enabled with the secondary core to resume an operation of the primary core.