US Patent:
20030182539, Sep 25, 2003
Inventors:
Steven Kunkel - Rochester MN, US
David Lilja - Maplewood MN, US
Resit Sendag - Minneapolis MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F009/00
Abstract:
It has been determined that, in a superscalar computer processor, executing load instructions issued along an incorrectly predicted path of a conditional branch instruction eventually reduces the number of cache misses observed on the correct branch path. Executing these wrong-path loads provides an indirect prefetching effect. If the processor has a small L1 data cache, however, this prefetching pollutes the cache causing an overall slowdown in performance. By storing the execution results of mispredicted paths in memory, such as in a wrong path cache, the pollution is eliminated. A wrong path cache can improve processor performance up to 17% in simulations using a 32 KB data cache. A fully-associative eight-entry wrong path cache in parallel with a 4 KB direct-mapped data cache allows the execution of wrong path loads to produce an average processor speedup of 46%. The wrong path cache also results in 16% better speedup compared to the baseline processor equipped with a victim cache of the same size. Thus, the execution and storage of loads that are known to be from a mispredicted branch path significantly improves the performance of aggressive computer processor designs. This effect is even more important as the disparity between the processor cycle time and the memory speed continues to increase.