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Ritesh D Sojitra

from Murphy, TX
Age ~50
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Also known as:
Ritesh Dhirajlal Sojitra, Ritesh Dhirjlal Sojitra, Ripesh Sojitra, Spitra Ritesh
Phone and address:
428 Dakota Dr, Plano, TX 75094
(972) 516-1738
Related to:
Rajiv SethRonald Morrison, 56Terence Smith, 60Mose SmithSeth Ritesh, 43
Connected to:
Kajal T Sojitra, 39Ravi Sojitra, 31Barry J Sojka, 56Kayla R Sojka, 33Stanley A Sojka, 77Terrie E Sojka, 59Therese A Sojka, 36Dominika Sojko, 42Brisa M Sojo, 42Cristal M Sojo, 31

Ritesh Sojitra Phones & Addresses

  • 428 Dakota Dr, Murphy, TX 75094 (972) 516-1738
  • 1124 Coolidge St, Plano, TX 75094 (972) 516-1738
  • Sachse, TX
  • Sunnyvale, CA
  • 800 Renner Rd, Richardson, TX 75080 (972) 680-9156
  • Dallas, TX
  • Blacksburg, VA
  • Santa Clara, CA
  • Colton, TX

Work

Company: Texas instruments May 2002 Position: Hardware design engineer

Education

Degree: Masters School / High School: Virginia Polytechnic Institute and State University 1996 to 1998 Specialities: Electrical and Computer Engineering

Skills

ASIC • Verilog • EDA • TCL • SoC • VHDL • Debugging • NCSim • Primetime • SERDES • Static Timing Analysis • DFT • RTL coding • RTL design • Functional Verification • ModelSim • Integrated Circuit Design • IC • VLSI • Logic Synthesis • RTL verification • Timing Closure • Semiconductors • Synopsys tools • Cadence • ATPG • Hardware Architecture • Logic Design • DDR3

Industries

Semiconductors

Public records

Vehicle Records

Ritesh D Sojitra

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Address:
428 Dakota Dr, Murphy, TX 75094
VIN:
5FNRL38447B018293
Make:
HOND
Model:
RL38
Year:
2007

Resumes

Resumes

Ritesh Sojitra Photo 1

Hardware Design Engineer At Texas Instruments

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Position:
Hardware Design Engineer at Texas Instruments
Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Work:
Texas Instruments since May 2002
Hardware Design Engineer
Fujitsu Network Communications Aug 1998 - May 2002
ASIC Design Engineer
Education:
Virginia Polytechnic Institute and State University 1996 - 1998
Masters, Electrical and Computer Engineering Birla Vishvakarma Mahavidyalaya 1991 - 1995
Bachelor, Electrical Engineering
Skills:
ASIC
Verilog
EDA
TCL
SoC
VHDL
Debugging
NCSim
Primetime
SERDES
Static Timing Analysis
DFT
RTL coding
RTL design
Functional Verification
ModelSim
Integrated Circuit Design
IC
VLSI
Logic Synthesis
RTL verification
Timing Closure
Semiconductors
Synopsys tools
Cadence
ATPG
Hardware Architecture
Logic Design
DDR3

Publications

Us Patents

Receive Timing Manager

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US Patent:
8130889, Mar 6, 2012
Filed:
Apr 4, 2005
Appl. No.:
11/098130
Inventors:
Denis Roland Beaudoin - Rowlett TX, US
Ritesh Dhirajlal Sojitra - Plano TX, US
Gregory Lee Christison - McKinney TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 7/02
US Classification:
375360, 375316, 375355, 375354, 375359
Abstract:
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

Synchronized Voltage Scaling And Device Calibration

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US Patent:
20120084575, Apr 5, 2012
Filed:
Aug 25, 2011
Appl. No.:
13/218116
Inventors:
Jose Luis Flores - Richardson TX, US
Lewis Nardini - Richardson TX, US
Ritesh Sojitra - Plano TX, US
Denis Roland Beaudoin - Rowlett TX, US
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.

Receive Timing Manager

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US Patent:
20120121051, May 17, 2012
Filed:
Jan 25, 2012
Appl. No.:
13/358183
Inventors:
Denis Roland Beaudoin - Rowlett TX, US
Ritesh Dhirajlal Sojitra - Plano TX, US
Gregory Lee Christison - McKinney TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 7/033
H03L 7/00
US Classification:
375360, 327152
Abstract:
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

System And Method For Communications Link Calibration Using A Training Packet

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US Patent:
6578153, Jun 10, 2003
Filed:
Mar 16, 2000
Appl. No.:
09/527323
Inventors:
Wayne Robert Sankey - Plano TX
Kyl Scott - Richardson TX
Osman Koyuncu - Plano TX
Kam-Wing Li - Richardson TX
Ritesh Dhirajlal Sojitra - Dallas TX
Assignee:
Fujitsu Network Communications, Inc. - Richardson TX
International Classification:
H04L 700
US Classification:
713400, 710 71
Abstract:
In one aspect, the present invention provides a method of communicating across a serial line. In this method, n parallel streams of data are to be received at a destination. In a first embodiment, the n parallel streams of data characterized in that one of streams of data includes a unique characteristic that can be used to distinguish that one from each of the other streams of data. In a second embodiment, each of the n streams of data are in a particular pattern that includes a detectable characteristic. At the destination , the unique characteristic and/or detectable characteristic can be detected to correct space and/or time errors in the streams of data. For example, the destination might be a receiver that includes a serial-to-parallel converter and calibration circuitry.

Method And System For In-Line Ecc Protection

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US Patent:
20210406171, Dec 30, 2021
Filed:
Sep 14, 2021
Appl. No.:
17/474141
Inventors:
- Dallas TX, US
Ritesh Dhirajlal SOJITRA - Murphy TX, US
Samuel Paul VISALLI - Allen TX, US
International Classification:
G06F 12/02
G06F 12/0879
G11C 29/00
G11C 11/409
G11C 29/42
G06F 13/40
Abstract:
A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Method And System For In-Line Ecc Protection

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US Patent:
20200183826, Jun 11, 2020
Filed:
Oct 2, 2019
Appl. No.:
16/590515
Inventors:
- Dallas TX, US
Ritesh Dhirajlal SOJITRA - Murphy TX, US
Samuel Paul VISALLI - Allen TX, US
International Classification:
G06F 12/02
G06F 12/0879
G06F 13/40
G11C 11/409
G11C 29/42
G11C 29/00
Abstract:
A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.
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Ritesh D Sojitra from Murphy, TX, age ~50 Get Report