Robert Arlen Lasater

20170046293, Feb 16, 2017

Aug 10, 2015

14/822672

- Plano TX, US
Robert LASATER - Menlo Park CA, US

G06F 13/40
G06F 13/42

Systems and methods for analyzing a PCIe network using a graph-theory based analysis are disclosed. A management CPU is coupled to the root complex of the PCIe system and is operable to survey potential CPU-resource combinations in a PCIe system and assign a group of PCIe resources to a CPU. A first switch and a second switch are coupled to the root node, and a first CPU and a first group of PCIe resources are coupled to the first switch. The management CPU assigns a group of PCIe resources to a CPU based on the isolation of the first and second CPUs or a distance between the first and second CPUs and the groups of PCIe resources. According to some embodiments, for potential pairs of devices and NTB/CPUs, the distance between components is assessed, possible alternative paths are identified, and the isolation of the pair is determined.

20170024340, Jan 26, 2017

Oct 7, 2016

15/287985

- Plano TX, US
Robert LASATER - Menlo Park CA, US
Thomas BOYLE - Santa Clara CA, US
John PETERS - Sunnyvale CA, US
Guangyu SHI - Cupertino CA, US

Futurewei Technologies, Inc. - Plano TX

G06F 13/24
G06F 13/40
G06F 13/42

An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

20160352651, Dec 1, 2016

Aug 15, 2016

15/236636

- Plano TX, US
Robert LASATER - Menlo Park CA, US
Guangyu SHI - Cupertino CA, US
Thomas BOYLE - Plano CA, US

Futurewei Technologies, Inc. - Plano TX

H04L 12/947
H04L 12/707
H04L 12/933
H04L 12/24

In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

20160134564, May 12, 2016

Nov 7, 2014

14/536516

- Plano TX, US
Robert LASATER - Menlo Park CA, US
Guangyu SHI - Cupertino CA, US

H04L 12/947
H04L 12/707
H04L 12/24
H04L 12/933

The descriptions presented herein include explanation of high-dimensional PCI-Express (PCIe) network implementations. The new approaches can facilitate utilization of an efficient protocol (e.g., PCIe, etc.) while enabling implementation of various characteristics and features (e.g., characteristics and features similar to a fat-tree topology, CLOS topology, 2D and 3D topologies, etc.) that would otherwise not be compatible with the protocol. For example, implementation of alternative paths can be enabled and utilized while maintaining compliance with a protocol (e.g., PCIe, etc.) that would otherwise not be compatible with the use of alternative paths. The alternative paths can facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. In one embodiment, presented systems and methods facilitate utilization of a non-transparent bridge circuit configured as an end-point with respect to communications from at least one device while facilitating transmission of the communications on to at least one other device.

20150143016, May 21, 2015

Nov 18, 2013

14/083206

- Plano TX, US
Robert LASATER - Menlo Park CA, US
Thomas BOYLE - Santa Clara CA, US
John PETERS - Sunnyvale CA, US
Guangyu SHI - Cupertino CA, US

Futurewei Technologies, Inc. - Plano TX

G06F 13/32
G06F 13/42

710313, 710269

An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

20150026385, Jan 22, 2015

Jun 25, 2014

14/315099

- Plano TX, US
Robert LASATER - Menlo Park CA, US
Thomas BOYLE - Santa Clara CA, US
John PETERS - Sunnyvale CA, US
Guangyu SHI - Cupertino CA, US

FUTUREWEI TECHNOLOGIES, INC. - Plano TX

G06F 9/50
G06F 13/16

710314

Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.