Ronald E Dammann

6993032, Jan 31, 2006

Jun 29, 2000

09/606025

Ronald Dammann - Palo Alto CA, US
James A. McConnell - Sunnyvale CA, US

Intel Corporation - Santa Clara CA

H04L 12/28
H04L 12/56

3703957, 370412, 711170

The present invention is directed to buffer arrangements (e. g. , via concatenation) to support differential link distances at full bandwidth.

7233996, Jun 19, 2007

Nov 12, 2002

10/293170

Narayanan G. Kaniyur - Newark CA, US
Ronald L. Dammann - Palo Alto CA, US

Intel Corporation - Santa Clara CA

G06F 13/00

709227, 709232, 709237, 709250

In one embodiment, a method is provided. In the method of this embodiment, one operating mode of port circuitry may be selected from a plurality of operating modes of the port circuitry that may correspond to respective sets of one or more communication links via which the port circuitry may be capable of communicating when the port circuitry is operating in the respective operating modes. Each of the respective sets of one or more communication links may be different from each other. The method of this embodiment also may include selecting, based at least in part upon the one operating mode of the port circuitry, a set of filters. The port circuitry may be capable of determining, based at least in part upon the set of filters, whether to drop a packet that is received, or intended to be transmitted by the port circuitry.

7346064, Mar 18, 2008

Sep 26, 2002

10/255419

Percy K. Wadia - Sunnyvale CA, US
Ronald L. Dammann - Palo Alto CA, US
James A. McConnell - Longmont CO, US

Intel Corporation - Santa Clara CA

H04L 12/28
H04L 12/56
H04J 1/16
H04J 3/14
G06F 11/00
G08C 15/00

370401, 370229

An interconnect device (e. g. , a switch) includes a port operably coupled to a packet broadcaster for routing unicast and/or multicast packets of data in packet-based input/output communications. For an inbound packet, at least two combinations of a source port and one or more destination ports, and one or more destination paths associated with each of said one or more destination ports may be determined by the packet broadcaster in a single lookup of a memory (e. g. , a random access memory).

7519060, Apr 14, 2009

Mar 19, 2003

10/391961

David C. Nadell - San Jose CA, US
Satishkumar P. Sampath - Milpitas CA, US
Ronald L. Dammann - Palo Alto CA, US

Intel Corporation - Santa Clara CA

H04L 12/28
H04L 12/56

370390, 370389, 370391

In one embodiment, an interconnect device (e. g. , a switch) includes an interface operably coupled to an interconnect logic capable of reducing inter-packet gaps in packet -based input/output communications. Based on, at least in part, a packet attribute associated with an inbound packet, the interconnect logic may determine an indication of transfer grant which may be issued in conjunction with a packet relay request, sending packet attribute information in advance of the packet attribute.

7523378, Apr 21, 2009

Sep 23, 2005

11/233742

Ronald L. Dammann - Palo Alto CA, US
Steven R. King - Portland OR, US
Frank L. Berry - North Plains OR, US

Intel Corporation - Santa Clara CA

H03M 13/00

714758

Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and the integrity checking operations may include determination of a cyclical redundancy checking (CRC) value.

8525600, Sep 3, 2013

Oct 25, 2011

13/281369

Robert S. Vendryes - Aurora CO, US
Ericka Sleight - Mountain View CA, US
Donald L. Davis - Milpitas CA, US
Jerome Chang - San Jose CA, US
Jack L. Mix - Livermore CA, US
Ronald Dammann - San Jose CA, US

Lockheed Martin Corporation - Bethesda MD

H03B 5/32
H01L 41/053

331 68, 331158, 310344, 310348

A protective assembly that is adapted to provide temperature isolation for an electronic device is disclosed. The assembly includes a housing having a cavity with a top surface and at least one side surface. The housing is configured to accept an electronic device having a top and a bottom in the cavity with the top of the electronic device proximate to the top surface of the cavity. The housing is further configured to maintain a vacuum within the cavity. The assembly includes at least one support disposed within the cavity. The at least one support is configured to contact the housing only at a first point proximate to the top surface of the cavity and contact the electronic device only at a second point that is proximate to the bottom of the electronic device.

20070061549, Mar 15, 2007

Sep 15, 2005

11/228687

Narayanan Kaniyur - Newark CA, US
Perey Wadia - Sunnyvale CA, US
Debendra Sharma - Santa Clara CA, US
Ronald Dammann - Palo Alto CA, US

G06F 12/00

711207000

A method and an apparatus to track address translation in I/O virtualization have been presented. In one embodiment, the method includes initiating a page walk if none of a plurality of entries in a translation lookaside buffer (TLB) in a direct memory access (DMA) remap engine matches a guest physical address of an incoming address translation request. The method further includes performing the page walk in parallel with one or more ongoing page walks and tracking progress of the page walk using one or more of a plurality of flags and state information pertaining to intermediate states of the page walk stored in the TLB. Other embodiments have been claimed and described.

20070067505, Mar 22, 2007

Sep 22, 2005

11/233783

Narayanan Kaniyur - Newark CA, US
Alexander Brown - Mountain View CA, US
Percy Wadia - Sunnyvale CA, US
Ronald Dammann - Palo Alto CA, US

G06F 13/28

710022000

A method and an apparatus to prevent over subscription and thrashing of translation lookaside buffer (TLB) entries in I/O virtualization hardware have been presented. In one embodiment, the method includes performing address translation in a direct memory access (DMA) remap engine within an input/output (I/O) hub in response to I/O requests from a root port using a guest physical address (GPA) queue to temporarily hold address translations requests to service the I/O requests and a TLB. The method may further include managing allocation of entries in the TLB to the address translation requests using an allocation window to avoid over-subscription of the entries and managing de-allocation of the entries using a de-allocation window to avoid thrashing of the entries. Other embodiments have been claimed and described.