Ronald Charles Laugesen

46412476, Feb 3, 1987

Aug 30, 1985

6/771387

Ronald C. Laugesen - Los Gatos CA
Padmanabha I. Venkitakrishnan - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1560

364490

A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention. The bit-slice organization of the chip significantly reduces the design effort of the components connected to a bus, since a one-bit slice is merely replicated for each conductor of the bus.

40499790, Sep 20, 1977

Aug 24, 1976

5/717428

Mark S. D. Shieu - San Jose CA
Robert B. Johnson - Los Gatos CA
Ronald C. Laugesen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 1710
H03K 458
H03K 1728
H03K 1940

307270

Plural bootstrap capacitors are coupled to an output stage of a MOSFET driver. A conventional bootstrap driver is preceded by one or more additional bootstrap stages. Each one includes a capacitor, a tri state inverter and a delay section. When the output stage is off all capacitors are discharged. To turn the output stage on, all capacitors, including the output gate capacitance, are charged in parallel. Then each capacitor in turn is caused to pump its charge into the gate of the output stage, with the last capacitor pumping the output stage gate voltage to a level well in excess of the applied power supply voltage.

40485242, Sep 13, 1977

Apr 21, 1976

5/679120

Ronald C. Laugesen - Sunnyvale CA
Mark Shin-Dong Shieu - San Jose CA

National Semiconductor Corporation - Santa Clara CA

H03K 5153
H03K 3295
H03K 3353
H03K 1730

307304

In a MOS integrated circuit, a voltage level detecting and indicating circuit apparatus is provided. In the apparatus there is provided a MOS integrated circuit means responsive to a change in the magnitude of a voltage in the circuit. In the circuit means there is provided a first node at which occurs a first signal when the magnitude of the voltage is changed to a first predetermined magnitude, said occurrence of said first signal being independent of at least one of a plurality of process variables including threshold voltage, mobility, body effect factor and lateral diffusion within a predetermined range of magnitude of said variable, and a second node at which occurs a second signal when said magnitude of said voltage is changed to a second predetermined magnitude and a third signal when said magnitude of said voltage is changed to the third predetermined magnitude, said occurrence of said second and third signals being dependent on at least one of said plurality of process variables.

41248082, Nov 7, 1978

Jan 28, 1977

5/763380

Mark S. D. Shieu - San Jose CA
Ronald C. Laugesen - Sunnyvale CA
Robert C. Dobkin - Hillsborough CA

National Semiconductor Corporation - Santa Clara CA

H03K 102
H03K 518

307362

A comparator amplifier circuit is integrated in MOS form. A sense amplifier section is coupled to a buffer amplifier section to provide an output that changes sharply at a particular voltage input. A compensating amplifier section is coupled between the comparator amplifier and a node in the buffer amplifier so that the voltage sense is independent of integrated circuit manufacturing variables.

39952320, Nov 30, 1976

May 2, 1975

5/573912

Ronald C. Laugesen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03B 512

331111

An integrated circuit oscillator includes a timing circuit and a bistable circuit for controlling the timing circuit. The timing circuit includes a capacitor and a pair of field effect transistors (FET), one of which is employed for charging the capacitor and the other of which is employed for discharging the capacitor. A first stage having a relatively low trip voltage is responsive to a low level of charge on the capacitor for actuating the bistable circuit to a first state and a second stage having a relatively high trip voltage is responsive to a high level of charge on the capacitor for actuating the bistable circuit to a second state. The charging and discharging FET's are rendered conductive in response to the first and second states, respectively, of the bistable circuit, such that the capacitor is both charged and discharged over relatively long time periods. A pair of clamping circuits connected to the charging and discharging FET's reduce frequency variations which would normally occur with variations in process parameters and variations in the voltage level of the power supply.

40631176, Dec 13, 1977

Jan 7, 1977

5/757710

Ronald C. Laugesen - Sunnyvale CA
Ury Priel - Cupertino CA

National Semiconductor Corporation - Santa Clara CA

H03K 1712
H03K 1704
H03K 1728
H03K 1760

307270

In order to increase the output current of an MOS transistor, its gate is provided with a switched capacitor drive. A tri-state inverter is used to drive the output transistor gate from an input source. A pair of delay elements are cascaded to drive one input of a NOR gate, the other input of which is fed an undelayed signal. The NOR gate is used to switch a capacitor that is also coupled to the output transistor gate. The juncture between the delays is coupled to the control electrode of the tri-state inverter. During the first delay interval, the capacitor and the output transistor gate electrode are charged. Then after the second delay interval, which is shorter than the first, the capacitor is discharged into the output transistor gate electrode which is thereby driven substantially in excess of the conventional drive level.

47180579, Jan 5, 1988

Aug 30, 1985

6/771339

P. Venkitakrishnan - Sunnyvale CA
Gururaj Singh - Sunnyvale CA
Ronald C. Laugesen - Los Gatos CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H04J 110
H04J 302

370 55

An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals.

47714182, Sep 13, 1988

Jul 28, 1986

6/891438

Subramanian Narasimhan - Santa Clara CA
Ronald Laugesen - Los Gatos CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H04Q 1104
H04J 312

370 58

For each channel, a pair of buffers permits "non-slip" transfer of data signals on and off a bus synchronized with signals on a time-division multiplexed pulse-code modulation (PCM) highway. A source buffer consisting of a serial-in, parallel-out register and two parallel-in, parallel-out registers receives signals from one of the PCM channels and transmits these signals onto a bus synchronized with a data-routing multiplexer employed within a digital exchange controller employing the device. A destination buffer consisting of two parallel-in, parallel-out registers and a parallel-in, serial-out register receives signal from the bus and, in conjunction with a transmit multiplexer, generates the signals on the PCM highway.