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Ryan C Kivimagi

from Chatfield, MN
Age ~48
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Also known as:
Ryan D Kivimagi, Ryan I, Red I
Phone and address:
1772 3Rd St, Cummingsville, MN 55923
(507) 867-2961
Related to:
John L Snow, 61Karen BaileyRichard KivimagiRichard Bailey, 64Cadi GCarol Kivimagi, 71
Connected to:
Ain H Kivimae, 86Dawn A Kivimaki, 76Gavin V Kivinen, 41Aimee M Kiviniemi, 45Matthew Kiviniemi, 45Shelley R Kivipelto, 66Nicole V Kivirtzikis, 46Deborah L Kivisalu, 65Cindy K Kivisto, 71Jeannine A Kivisto, 71

Ryan Kivimagi Phones & Addresses

  • 1772 3Rd St, Chatfield, MN 55923 (507) 867-2961
  • 719 Grand St, Chatfield, MN 55923
  • 7195 Grand St, Chatfield, MN 55923
  • 4404 5Th St, Rochester, MN 55901
  • 528 Welch Ave, Ames, IA 50014

Work

Company: Ibm Jun 2018 Position: Manager analog circuits

Education

Degree: Master of Business Administration, Masters School / High School: Cardinal Stritch University 2001 to 2003

Skills

Hardware • Team Leadership • Unix • Testing • Perl • Sql • Layout • Php • Microsoft Office • Problem Solving • Excel • Powerpoint • Word • Shell Scripting • Physical Design • Asic • Vlsi • Dft • Vhdl • Array Design • Linux • Plc Programming • Software Development • Ic • Integration • Cmos • Hardware Architecture • Adobe Illustrator • Apple Script • Debugging • Functional Verification • Circuit Design • Verilog • Tcl • Computer Architecture • Soc

Languages

English

Interests

Health

Industries

Semiconductors

Resumes

Resumes

Ryan Kivimagi Photo 1

Manager Analog Circuits

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Location:
4404 5Th St northwest, Rochester, MN 55901
Industry:
Semiconductors
Work:
Ibm
Manager Analog Circuits
Ibm Jan 1999 - Jun 2018
Senior Am Designer
Ibm Jan 1999 - Jun 2018
Electrical Engineer
Abb 1995 - 1997
Engineer
Education:
Cardinal Stritch University 2001 - 2003
Master of Business Administration, Masters Iowa State University 1994 - 1998
Bachelors, Bachelor of Science, Electrical Engineering, Engineering The Chosen Valley High School 1990 - 1994
Skills:
Hardware
Team Leadership
Unix
Testing
Perl
Sql
Layout
Php
Microsoft Office
Problem Solving
Excel
Powerpoint
Word
Shell Scripting
Physical Design
Asic
Vlsi
Dft
Vhdl
Array Design
Linux
Plc Programming
Software Development
Ic
Integration
Cmos
Hardware Architecture
Adobe Illustrator
Apple Script
Debugging
Functional Verification
Circuit Design
Verilog
Tcl
Computer Architecture
Soc
Interests:
Health
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
1772 3Rd St SW, Chatfield, MN 55923
107 1St St SW, Chatfield, MN 55923
107 1St St SW, Chatfield, MN 55923
Ryan Kivimagi
Owner
Discount Lettering Brands
Mfg Signs/Advertising Specialties
1772 3 St SW, Cummingsville, MN 55923
Ryan Kivimagi
Owner
Half Price Buttons
Signs
107 1 St SW, Chatfield, MN 55923
(866) 227-2480, (800) 476-4804
Ryan Kivimagi
Principal
Sign Factory, Inc
Mfg Signs/Advertising Specialties
1772 3 St SW, Cummingsville, MN 55923
Ryan Kivimagi
Timberland Wholesale
Internet Marketing Services · Internet Shopping
1772 3 St SW, Chatfield, MN 55923
(507) 261-3126

Publications

Us Patents

Flood Mode Implementation For Continuous Bitline Local Evaluation Circuit

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US Patent:
7133320, Nov 7, 2006
Filed:
Nov 4, 2004
Appl. No.:
10/981153
Inventors:
Chad Allen Adams - Byron MN, US
Derick Gardner Behrends - Rochester MN, US
Ryan Charles Kivimagi - Chatfield MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365201, 365203
Abstract:
A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Maskable Dynamic Logic

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US Patent:
7215154, May 8, 2007
Filed:
Jul 21, 2005
Appl. No.:
11/186608
Inventors:
Derick Gardner Behrends - Rochester MN, US
Ryan Charles Kivimagi - Chatfield MN, US
Chihhung Liao - Fremont CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19/096
US Classification:
326 97, 326 95
Abstract:
An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.

Glitch Protect Valid Cell And Method For Maintaining A Desired State Value

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US Patent:
7224594, May 29, 2007
Filed:
Jul 19, 2005
Appl. No.:
11/184346
Inventors:
Derick G. Behrends - Rochester MN, US
Chad A. Adams - Rochester MN, US
Ryan C. Kivimagi - Rochester MN, US
Anthony G. Aipperspach - Rochester MN, US
Robert N. Krentler - Austin TX, US
Assignee:
International Business Machines - Armonk NY
International Classification:
G11C 15/00
US Classification:
365 49, 365233, 36518911, 711108
Abstract:
A glitch protect valid cell and method for maintaining a desired logic state value. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit. The glitch protect circuit includes a propagation delay assembly coupled to a restore assembly. The propagation delay assembly includes a first pull down network coupled to a NOR gate. The restore assembly includes a second pull down network coupled to the propagation delay assembly. Responsive to a glitch signal and timing signal, the first pull down network resets the initial state value of a true valid bit to ultimately enable a pull up network in the NOR gate. Responsive to enablement of the NOR gate pull up network, the second pull down network resets the complement valid bit in the memory element to consequently restore the initial state of the true valid bit.

Flood Mode Implementation For Continuous Bitline Local Evaluation Circuit

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US Patent:
7283411, Oct 16, 2007
Filed:
Oct 25, 2006
Appl. No.:
11/552791
Inventors:
Chad Allen Adams - Byron MN, US
Derick Gardner Behrends - Rochester MN, US
Ryan Charles Kivimagi - Chatfield MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365201, 365154, 365203
Abstract:
A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Methods And Apparatus For Testing Integrated Circuits

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US Patent:
7418637, Aug 26, 2008
Filed:
Aug 7, 2003
Appl. No.:
10/636060
Inventors:
Derick G. Behrends - Rochester MN, US
Peter T. Freiburger - Rochester MN, US
Ryan C. Kivimagi - Chatfield MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
In some aspects a method is provided for testing an integrated circuit (IC). The method includes the steps of selecting a bit from each of a plurality of memory arrays formed on an IC chip, selecting one of the plurality of memory arrays, and storing the selected bit from the selected memory array. Numerous other aspects are provided.

Method For Reducing Wiring And Required Number Of Redundant Elements

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US Patent:
7443744, Oct 28, 2008
Filed:
Nov 14, 2006
Appl. No.:
11/559431
Inventors:
Derick Gardner Behrends - Rochester MN, US
Peter Thomas Freiburger - Rochester MN, US
Ryan Charles Kivimagi - Chatfield MN, US
Daniel Mark Nelson - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365200, 365 63, 36523002
Abstract:
A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

Methods And Apparatus For Testing Integrated Circuits

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US Patent:
7681095, Mar 16, 2010
Filed:
Jul 9, 2008
Appl. No.:
12/170213
Inventors:
Derick G. Behrends - Rochester MN, US
Peter T. Freiburger - Rochester MN, US
Ryan C. Kivimagi - Chatfield MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
In some aspects, an apparatus is provided. The apparatus includes a plurality of memory arrays, a latch, and a selection circuit coupled to the plurality of memory arrays and to the latch. The selection circuit may be operative to receive a bit from each of a plurality of memory arrays select one of the plurality of memory arrays, and store the bit from the selected memory array. Numerous other aspects are provided.

Methods And Apparatus For Writing An Lru Bit

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US Patent:
20050125615, Jun 9, 2005
Filed:
Dec 4, 2003
Appl. No.:
10/728300
Inventors:
Peter Freiburger - Rochester MN, US
Ryan Kivimagi - Chatfield MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
G06F013/00
US Classification:
711160000
Abstract:
In a first aspect, a first method is provided for writing an LRU indicator. The first method includes the steps of (1) activating one of a first word line that corresponds to a first memory array and a second word line which corresponds to a second memory array; (2) employing the first word line, when activated, for writing to the first memory array and for writing the LRU indicator; and (3) employing the second word line, when activated, for writing to the second memory array and for writing the LRU indicator. Numerous other aspects are provided.
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Ryan C Kivimagi from Chatfield, MN, age ~48 Get Report