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Sameer Shekhar

from Portland, OR
Age ~41
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Connected to:
Naveen Shekhar, 41Megha Shekhawat, 35Nakul S Shekhawat, 37Vijay Shekhawat, 43Yacoub Shekhayem, 52Aleksandr B Shekhel, 75Tatyana A Shekhel, 43Khachik A Shekherdimian, 71Tetiana Shekhovtsova, 65Tatyana Shekhterman, 48

Sameer Shekhar Phones & Addresses

  • 2974 NW 110Th Ter, Portland, OR 97229
  • Beaverton, OR
  • Tempe, AZ

Resumes

Resumes

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Engineer

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Location:
Portland, OR
Industry:
Electrical/Electronic Manufacturing
Work:
Intel Corporation
Engineer
Maxlinear May 2010 - Jul 2010
Field Application Engineer
Arizona State University May 2008 - Apr 2010
Research Assistant
Cognizant Technology Solutions Sep 2006 - Jul 2007
Programmer Analyst
Education:
Arizona State University 2007 - 2010
Master of Science, Masters, Electrical Engineering R. V. College of Engineering, Bangalore 2002 - 2006
Bachelors, Telecommunications, Engineering
Skills:
Simulations
Semiconductors
Pcb Design
Analog
Cadence Virtuoso
Microwave
Electromagnetics
Analog Circuit Design
Sameer Shekhar Photo 2

Sameer Shekhar

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Sameer Shekhar Photo 3

Sameer Shekhar

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Publications

Us Patents

Stacked Semiconductor Package And Method Of Forming The Same

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US Patent:
20210384135, Dec 9, 2021
Filed:
Aug 7, 2020
Appl. No.:
16/987440
Inventors:
- Santa Clara CA, US
Bok Eng CHEAH - Gelugor Pulau Pinang, MY
Jackson Chung Peng KONG - Tanjung Tokong Pulau Pinang, MY
Sameer SHEKHAR - Portland OR, US
Amit JAIN - Sherwood OR, US
International Classification:
H01L 23/538
H01L 23/00
H01L 21/48
Abstract:
According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

Embedded Bridge Substrate Having An Integral Device

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US Patent:
20210335712, Oct 28, 2021
Filed:
Jul 9, 2021
Appl. No.:
17/371293
Inventors:
- Santa Clara CA, US
Sameer Shekhar - Portland OR, US
Chin Lee Kuan - Bentong, MY
Kevin Joseph Doran - North Plains OR, US
Dong-Ho Han - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/538
H01L 49/02
H01L 23/00
Abstract:
Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

Digital Linear Regulator Clamping Method And Apparatus

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US Patent:
20210208656, Jul 8, 2021
Filed:
Jan 6, 2020
Appl. No.:
16/735563
Inventors:
- Santa Clara CA, US
Eugene Gorbatov - Hillsboro OR, US
Harish Krishnamurthy - Beaverton OR, US
Alexander Lyakhov - Portland OR, US
Patrick Leung - Portland OR, US
Stephen Gunther - Beaverton OR, US
Arik Gihon - Rishon Le Zion, IL
Khondker Ahmed - Hillsboro OR, US
Philip Lehwalder - Hillsboro OR, US
Sameer Shekhar - Portland OR, US
Vishram Pandit - Bangalore, IN
Nimrod Angel - Haifa, IL
Michael Zelikson - Haifa, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
G05F 1/56
Abstract:
A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Package Edge Mounted Frame Structures

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US Patent:
20200098674, Mar 26, 2020
Filed:
Sep 26, 2018
Appl. No.:
16/142249
Inventors:
- Santa Clara CA, US
Amit Kumar Jain - Portland OR, US
Sameer Shekhar - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/498
H01L 25/065
H01L 23/00
H01L 21/48
Abstract:
Embodiments may relate to a semiconductor package. A conductive frame may be coupled with the semiconductor package. The conductive frame may include a first portion, a second portion, and a third portion positioned between the first portion and the second portion. The first portion may be coupled with the first side of the semiconductor package. The second portion may be coupled with the second side of the semiconductor package. The third portion may be coupled with the sidewall of the semiconductor package. Other embodiments may be described or claimed.

Device, Method And System To Mitigate A Voltage Overshoot Event

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US Patent:
20200007039, Jan 2, 2020
Filed:
Jun 28, 2018
Appl. No.:
16/021712
Inventors:
Amit Jain - Portland OR, US
Sameer Shekhar - Portland OR, US
Alexander Lyakhov - Portland OR, US
Jonathan Douglas - Portland OR, US
Vivek Saxena - San Ramon CA, US
International Classification:
H02M 3/158
Abstract:
Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

Per Chiplet Thermal Control In A Disaggregated Multi-Chiplet System

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US Patent:
20190384367, Dec 19, 2019
Filed:
Aug 26, 2019
Appl. No.:
16/551523
Inventors:
- Santa Clara CA, US
Sameer Shekhar - Portland OR, US
Mark Carbone - Cupertino CA, US
Merwin M. Brown - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/20
G06F 1/3206
G06F 1/324
G06F 1/3296
Abstract:
Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.

Input Voltage Protection

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US Patent:
20190377405, Dec 12, 2019
Filed:
Mar 29, 2019
Appl. No.:
16/369529
Inventors:
- Santa Clara CA, US
Eugene Gorbatov - Hillsboro OR, US
Philip R. Lehwalder - Hillsboro OR, US
Michael Zelikson - Haifa, IL
Sameer Shekhar - Portland OR, US
Nimrod Angel - Haifa, IL
Jonathan Douglas - Portland OR, US
Muhammad Abozaed - Haifa, IL
Alan Hallberg - North Plains OR, US
Douglas Huard - Portland OR, US
Edward Burton - Hillsboro OR, US
Merwin Brown - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/3296
G06F 1/3206
G05F 1/625
Abstract:
In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.

Magnetic Sensing Scheme For Voltage Regulator Circuit

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US Patent:
20190312513, Oct 10, 2019
Filed:
Jun 25, 2019
Appl. No.:
16/452322
Inventors:
Amit Kumar Jain - Portland OR, US
Chin Lee Kuan - Bentong, MY
Sameer Shekhar - Portland OR, US
International Classification:
H02M 3/158
H01F 27/28
H01F 27/40
G06F 1/26
G01R 19/165
Abstract:
Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.
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Sameer Shekhar from Portland, OR, age ~41 Get Report