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Srabanti S Chowdhury

from Palo Alto, CA
Age ~45
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Related to:
Sukla ChowdhuryPrabir K ChakrabortyArati ChakrabortyArpan Chakraborty, 47
Connected to:
Adbur R Chowdhury, 67Akhtari K Chowdhury, 59Amirul I Chowdhury, 36Ankush Chowdhury, 43Arefeen Chowdhury, 41Arefur R Chowdhury, 36Arifa A Chowdhury, 52Asad U Chowdhury, 37Ashea A Chowdhury, 60Atusha Chowdhury, 34

Srabanti Chowdhury Phones & Addresses

  • Palo Alto, CA
  • 807 Henley Ct, San Ramon, CA 94583
  • Santa Clara, CA
  • Chandler, AZ
  • Goleta, CA

Work

Company: Stanford university Jan 2019 Position: Associate professor

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Uc Santa Barbara 2006 to 2010 Specialities: Electrical Engineering

Skills

Semiconductors • Power Electronics • Thin Films • Nanotechnology • Simulations • Photolithography • Semiconductor Industry • Characterization • Physics • Materials Science • Failure Analysis • Device Characterization • Afm • Cvd • Metrology • Optoelectronics • Ic • Silicon • Semiconductor Device • Design of Experiments • Jmp

Industries

Semiconductors

Resumes

Resumes

Srabanti Chowdhury Photo 1

Associate Professor

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Location:
522 north Central Ave, Phoenix, AZ 85001
Industry:
Semiconductors
Work:
Stanford University
Associate Professor
Uc Davis Jul 2015 - Dec 2018
Associate Professor
Transphorm Inc. May 2010 - Mar 2013
Mts
Education:
Uc Santa Barbara 2006 - 2010
Doctorates, Doctor of Philosophy, Electrical Engineering
Skills:
Semiconductors
Power Electronics
Thin Films
Nanotechnology
Simulations
Photolithography
Semiconductor Industry
Characterization
Physics
Materials Science
Failure Analysis
Device Characterization
Afm
Cvd
Metrology
Optoelectronics
Ic
Silicon
Semiconductor Device
Design of Experiments
Jmp

Publications

Wikipedia References

Srabanti Chowdhury Photo 2

Srabanti Chowdhury

Us Patents

Transistors With Isolation Regions

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US Patent:
20120153390, Jun 21, 2012
Filed:
Dec 15, 2010
Appl. No.:
12/968704
Inventors:
Umesh Mishra - Montecito CA, US
Srabanti Chowdhury - Goleta CA, US
Assignee:
TRANSPHORM INC. - Goleta CA
International Classification:
H01L 29/78
H01L 23/62
US Classification:
257339, 257335, 257355, 257E23002, 257E29256
Abstract:
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.

Current Aperture Vertical Electron Transistors With Ammonia Molecular Beam Epitaxy Grown P-Type Gallium Nitride As A Current Blocking Layer

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US Patent:
20120319127, Dec 20, 2012
Filed:
Jun 20, 2012
Appl. No.:
13/527885
Inventors:
Srabanti Chowdhury - Goleta CA, US
Ramya Yeluri - Santa Barbara CA, US
Christophe Hurni - Goleta CA, US
Umesh K. Mishra - Montecito CA, US
Ilan Ben-Yaacov - Goleta CA, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA
International Classification:
H01L 29/20
H01L 21/20
US Classification:
257 76, 438478, 257E29089, 257E2109
Abstract:
A current aperture vertical electron transistor (CAVET) with ammonia (NH) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Semiconductor Devices With Guard Rings

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US Patent:
20130056744, Mar 7, 2013
Filed:
Sep 6, 2011
Appl. No.:
13/226380
Inventors:
Umesh Mishra - Montecito CA, US
Srabanti Chowdhury - Goleta CA, US
Yuvaraj Dora - Goleta CA, US
Assignee:
TRANSPHORM INC. - Goleta CA
International Classification:
H01L 29/778
H01L 21/329
H01L 29/872
H01L 21/338
US Classification:
257 76, 438172, 438571, 257183, 257E29252, 257E21403, 257E29338, 257E21359
Abstract:
Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.

High Power Semiconductor Electronic Components With Increased Reliability

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US Patent:
20130088280, Apr 11, 2013
Filed:
Oct 7, 2011
Appl. No.:
13/269367
Inventors:
Rakesh K. Lal - Isla Vista CA, US
Robert Coffie - Camarillo CA, US
Yifeng Wu - Goleta CA, US
Primit Parikh - Goleta CA, US
Yuvaraj Dora - Goleta CA, US
Umesh Mishra - Montecito CA, US
Srabanti Chowdhury - Goleta CA, US
Nicholas Fichtenbaum - Santa Barbara CA, US
Assignee:
TRANSPHORM INC. - Goleta CA
International Classification:
H01L 35/00
G05F 3/02
H01R 43/00
H01L 25/00
US Classification:
327513, 327566, 327543, 29825
Abstract:
An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

N-Polar Iii-Nitride Transistors

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US Patent:
20130264578, Oct 10, 2013
Filed:
Apr 9, 2013
Appl. No.:
13/859635
Inventors:
Umesh Mishra - Montecito CA, US
Srabanti Chowdhury - Goleta CA, US
Carl Joseph Neufeld - Goleta CA, US
Assignee:
TRANSPHORM INC. - Goleta CA
International Classification:
H01L 29/205
H01L 29/78
US Classification:
257 76, 257192
Abstract:
An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.

Semiconductor Devices With Integrated Hole Collectors

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US Patent:
20140001557, Jan 2, 2014
Filed:
Jun 27, 2012
Appl. No.:
13/535094
Inventors:
Umesh Mishra - Montecito CA, US
Srabanti Chowdhury - Goleta CA, US
Ilan Ben-Yaacov - Goleta CA, US
Assignee:
TRANSPHORM INC. - Goleta CA
International Classification:
H01L 29/772
H01L 21/336
US Classification:
257367, 257288, 438285, 257E29242, 257E21409
Abstract:
Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

Semiconductor Electronic Components With Integrated Current Limiters

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US Patent:
20140015066, Jan 16, 2014
Filed:
Jul 16, 2012
Appl. No.:
13/550445
Inventors:
Yifeng Wu - Goleta CA, US
Umesh Mishra - Montecito CA, US
Srabanti Chowdhury - Goleta CA, US
Assignee:
TRANSPHORM INC. - Goleta CA
International Classification:
H01L 27/088
US Classification:
257392, 257E27061
Abstract:
An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.

Current Generation From Radiation With Diamond Diode-Based Devices For Detection Or Power Generation

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US Patent:
20200119207, Apr 16, 2020
Filed:
Oct 14, 2019
Appl. No.:
16/601038
Inventors:
- SCOTTSDALE AZ, US
- OAKLAND CA, US
Maitreya Dutta - Hillsboro OR, US
Manpuneet Benipal - Tempe AZ, US
Raghuraj Hathwar - Waltham MA, US
Ricardo O Alarcon - Chandler AZ, US
Srabanti Chowdhury - San Ramon CA, US
Stephen Goodnick - Fort McDowell AZ, US
Anna Zaniewski - Tempe AZ, US
Robert Nemanich - Scottsdale AZ, US
International Classification:
H01L 31/0288
H01L 31/115
Abstract:
Diamond diode-based devices are configured to convert radiation energy into electrical current, useable for sensing (i.e., detection) or delivery to a load (i.e., energy harvesting). A diode-based detector includes an intrinsic diamond layer arranged between p-type diamond and n-type diamond layers, with the detector further including at least one of (i) a boron containing layer arranged proximate to the n-type and/or the intrinsic diamond layers, or (ii) an intrinsic diamond layer thickness in a range of 10 nm to 300 microns. A diode-based detector may be operated in a non-forward biased state, with a circuit used to transmit a current pulse in a forward bias direction to reset a detection state of the detector. An energy harvesting device may include at least one p-i-n stack (including an intrinsic diamond layer between p-type diamond and n-type diamond layers), with a radioisotope source arranged proximate to the at least one p-i-n stack.
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Srabanti S Chowdhury from Palo Alto, CA, age ~45 Get Report