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Sreenivasan K Koduri

from Dallas, TX
Age ~56
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Also known as:
Sreenivasan Kalyani Koduri, Sreenivasa K Koduri, Sreenidasan Koduri, Sreeniva Koduri, Satyamurty Koduri, Koduri Sreenivasan, N Koduri, Julian Torres Herrera, Julian Herrera
Related to:
Vijaya K Koduri, 64Pedro Magana, 47Lydia HerreraBlanca E Sanchez, 39Susana Torres, 59
Connected to:
Anupama Koduri, 37Anurag Koduri, 27Aruna R Koduri, 66Bhargav Koduru, 38Rachel N Koduru, 36Subramania Koduvayur, 58Drake F Kodwyck, 73Joe Kody, 36Caleb Kodya, 27Lottie Kodyra, 86

Sreenivasan Koduri Phones & Addresses

  • Dallas, TX
  • 801 Legacy Dr, Plano, TX 75023 (972) 527-3351
  • 801 Legacy Dr #727, Plano, TX 75023 (972) 527-3351
  • 2023 Burnside Dr, Allen, TX 75013 (972) 390-0147
  • Aurora, CO
  • Colton, TX
  • 801 Legacy Dr APT 727, Plano, TX 75023 (972) 743-9417

Work

Company: Texas instruments Jan 2004 Position: Analog packaging technology manager,

Education

Degree: MS School / High School: Southern Methodist University 1989 to 1993 Specialities: Electrical Engineering

Skills

Semiconductors • Ic • Semiconductor Industry • Analog • Mixed Signal • Soc • Asic • Engineering Management • Cmos • Product Engineering • Failure Analysis • Electronics • Silicon • Simulations • Design of Experiments • Microelectronics • Analog Circuit Design • Circuit Design • Eda • Power Management • Hardware Architecture • Mems • Testing • Debugging • Pcb Design • Electrical Engineering • Digital Signal Processors • Rf • Integrated Circuit Design • Sensors • Integrated Circuits • System on A Chip • Jmp

Industries

Semiconductors

Resumes

Resumes

Sreenivasan Koduri Photo 1

Director, Analog And Power Technology Roadmapping

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments since Jan 2004
Analog Packaging Technology Manager,
Texas Instruments since Jan 1900
Fellow
Education:
Southern Methodist University 1989 - 1993
MS, Electrical Engineering The University of Texas at Dallas - School of Management 1900 - 1900
MBA, Marketing Southern Methodist University
Ph.D, Electrical Engineering The University of Texas at Dallas - School of Management
MS, Finance
Skills:
Semiconductors
Ic
Semiconductor Industry
Analog
Mixed Signal
Soc
Asic
Engineering Management
Cmos
Product Engineering
Failure Analysis
Electronics
Silicon
Simulations
Design of Experiments
Microelectronics
Analog Circuit Design
Circuit Design
Eda
Power Management
Hardware Architecture
Mems
Testing
Debugging
Pcb Design
Electrical Engineering
Digital Signal Processors
Rf
Integrated Circuit Design
Sensors
Integrated Circuits
System on A Chip
Jmp

Publications

Us Patents

Stepwise Autorotation Of Wire Bonding Capilliary

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US Patent:
6340112, Jan 22, 2002
Filed:
Jul 30, 1999
Appl. No.:
09/363849
Inventors:
Sreenivasan K. Koduri - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
B23K 3102
US Classification:
2281805, 228 45
Abstract:
A rotation device provides precise, stepwise rotation of a wire bonding capillary about the longitudinal axis of the capillary. This enables the capillary to be rotated to different angular alignments to perform wire bonding in different directions. The rotation device can be a click ring-type device, a cam-type device or any other device to provide stepwise rotation. At least a part of the rotation device is coupled to the capillary. Another part of the rotation device is separate from the capillary but engageable with the first part to provide rotation. Indicators may be positioned on the capillary to provide signals to detectors. The signals can be used to initially align the capillary and to realign the capillary during wire bonding. A computer may be used to provide automated control of the indicators and detectors, and automated rotation of the rotation device.

Automatic Detection Of Die Absence On The Wire Bonding Machine

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US Patent:
6510240, Jan 21, 2003
Filed:
May 9, 1995
Appl. No.:
08/437762
Inventors:
Sreenivasan Kalyani Koduri - Dallas TX
David Ho - Richardson TX
Yee Hsun U - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06K 900
US Classification:
382146, 382151
Abstract:
An apparatus detects the presence or absence of a semiconductor device. The apparatus includes a wire bonding machine to form a connection with the semiconductor device, and a camera to form an image of a position of the semiconductor device. A processor controls the wire bonding machine and transforms the image to pixel data. Additionally, the processor converts the pixel data to discrimination data to indicate whether the semiconductor device is present. The processor controls the wire bonding machine in accordance with the presence or the absence of the semiconductor device.

Method Of Controlling Bond Process Quality By Measuring Wire Bond Features

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US Patent:
6555401, Apr 29, 2003
Filed:
Aug 3, 2001
Appl. No.:
09/921811
Inventors:
Sreenivasan K. Koduri - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2166
US Classification:
438 18
Abstract:
A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond onto a bond pad of an integrated circuit by first obtaining a first image of said bond pad before bond attachment, then determining the coordinates of the center of said pad. Second, the bonder is instructed to attach a ball-shaped wire bond to the center of said pad. Next, a second image of said bond pad is obtained after bond attachment; this second image comprises an image of the ball-shaped portion of the bond and an image of the wire portion of said bond. The coordinates of the center of the ball-shaped portion of the bond are obtained by computer processing of the first and second images. The coordinates of the bond center and the pad center are compared, creating information for quality control of the bonder instruction and the bonding process. Finally, the bond process quality is controlled by inputting new bonder instruction for correcting any identified differences between the center coordinates.

System And Method To Recreate Illumination Conditions On Integrated Circuit Bonders

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US Patent:
6597963, Jul 22, 2003
Filed:
May 24, 2001
Appl. No.:
09/864576
Inventors:
Sreenivasan K. Koduri - Plano TX
David J. Bon - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21603
US Classification:
700121, 700125, 700 56, 700 57, 700109
Abstract:
A computerized system and method for recreating illumination conditions in a slave bonder, prepared to attach connecting bonds onto bond pads of a slave integrated circuit. First, images of illuminated alignment references of a master circuit on a master bonder are defined; these data are analyzed to construct relationships between reference images and bond locations; data and relationships are stored in a master file. Secondly, on a slave bonder, the master reference image data are regenerated so that the illumination conditions of the slave bonder, as based on images, are recreated. Thirdly, images of the slave circuit references are produced under the newly created illumination conditions, and the alignment references are compensated. Finally, the bonding locations of the slave circuit and the bonding program of the slave bonder are corrected so that connecting bonds can be attached onto the recomputed correct bond locations.

System And Method To Reduce Bond Program Errors Of Integrated Circuit Bonders

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US Patent:
6629013, Sep 30, 2003
Filed:
May 3, 2001
Appl. No.:
09/847905
Inventors:
Sreenivasan K. Koduri - Plano TX
David J. Bon - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G05B 1918
US Classification:
700121, 700 59, 700114, 2281805
Abstract:
A computerized system and method for reducing bond program errors in a slave bonder, prepared to attach connecting bonds onto bond pads of a slave integrated circuit, by first collecting, on a master bonder, input data concerning bond x-y locations, alignment reference x-y locations, and alignment reference images from a master integrated circuit, then analyzing these data to construct a network of relationships between reference images and bond locations, and store data and relationships in a master file. Secondly, on a slave bonder, all this information is automatically retrieved and compared by a computer with input data concerning alignment reference images from a slave circuit. Thirdly, any discrepancy found is corrected by a computer to identify the new bond locations on the slave circuit. Finally, the slave bonder attaches the connecting bonds based on the computed correct bond locations.

Back Side Coating Of Semiconductor Wafers

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US Patent:
6734532, May 11, 2004
Filed:
Dec 6, 2001
Appl. No.:
10/006576
Inventors:
Sreenivasan K. Koduri - Plano TX
Kenji Masumoto - Hiji Oita, JP
Mutsumi Masumoto - Beppu Oita, JP
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2358
US Classification:
257632, 257783, 438778
Abstract:
A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output pads suitable for metallurgical contacts. Further, the device has a protective plastic film (polyimide, epoxy resin, or silicone) of controlled and uniform thickness (20 to 60 m) selectively attached to the passive surface. The film is suitable to absorb light of visible and ultraviolet wavelengths, to remain insensitive to moisture absorption, and to exert thermomechanical stress on the chip such that this stress at least partially neutralizes the stress exerted by an outside part after chip assembly.

Bumpless Wafer Scale Device And Board Assembly

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US Patent:
6768210, Jul 27, 2004
Filed:
Nov 1, 2001
Appl. No.:
10/001302
Inventors:
Edgar R. Zuniga-Ortiz - McKinney TX
Sreenivasan K. Koduri - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2348
US Classification:
257781
Abstract:
A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.

Method Of Controlling Bond Process Quality By Measuring Wire Bond Features

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US Patent:
6789240, Sep 7, 2004
Filed:
Jan 2, 2003
Appl. No.:
10/335837
Inventors:
Sreenivasan K. Koduri - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 748
US Classification:
716 4, 382141, 382145, 382146, 382152
Abstract:
A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond onto a bond pad of an integrated circuit by first obtaining a first image of said bond pad before bond attachment, then determining the coordinates of the center of said pad. Second, the bonder is instructed to attach a ball-shaped wire bond to the center of said pad. Next, a second image of said bond pad is obtained after bond attachment; this second image comprises an image of the ball-shaped portion of the bond and an image of the wire portion of said bond. The coordinates of the center of the ball-shaped portion of the bond are obtained by computer processing of the first and second images. The coordinates of the bond center and the pad center are compared, creating information for quality control of the bonder instruction and the bonding process. Finally, the bond process quality is controlled by inputting new bonder instruction for correcting any identified differences between the center coordinates.
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Sreenivasan K Koduri from Dallas, TX, age ~56 Get Report