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Suman P Sah

from Colorado Springs, CO
Age ~37
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Related to:
Bindeshwar Sah
Connected to:
Dheeraj Sah, 45Jacob E Sah, 54Jimmy C Sah, 64Kanhai L Sah, 60Lay W Sah, 39Magdalene P Sah, 84Manju Sah, 36Rajiv K Sah, 39Si M Sah, 43Sujeet K Sah, 50

Suman Sah Phones & Addresses

  • 4002 Purple Plum Way, Colorado Spgs, CO 80920
  • Colorado Springs, CO
  • Vista, CA
  • Pullman, WA
  • Minneapolis, MN

Resumes

Resumes

Suman Sah Photo 1

Principal Rf And Ms Ic Design Engineer

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Location:
Pullman, WA
Industry:
Semiconductors
Work:
Maxlinear
Principal Rf and Ms Ic Design Engineer
Maxlinear
Senior Staff Rf and Ms Ic Design Engineer
Maxlinear
Staff Engineer
Washington State University Aug 2009 - Mar 2014
Graduate Research Assistant
Broadcom Feb 2012 - May 2012
Intern
Education:
Washington State University 2009 - 2014
Doctorates, Doctor of Philosophy, Design Indian Institute of Technology, Kharagpur 2004 - 2009
Masters, Bachelors, Vlsi Design, Communication, Engineering, Electronics
Skills:
Circuit Design
Cmos
Rf
Integrated Circuit Design
Phased Arrays
Bicmos
Signal Generation Circuits
Rf Dvt
Analog Circuit Design
Interests:
Electronics
Suman Sah Photo 2

Suman Sah

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Suman Sah Photo 3

Suman Sah

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Suman Sah Photo 4

Suman Sah

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Publications

Us Patents

Dynamic Element Matching

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US Patent:
20190341927, Nov 7, 2019
Filed:
May 6, 2019
Appl. No.:
16/403812
Inventors:
- Carlsbad CA, US
Suman Sah - Colorado Springs CO, US
International Classification:
H03M 1/66
H03M 7/16
G06F 7/58
Abstract:
A system comprises an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit comprises a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.

Multi-Ladder Digital To Analog Converter

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US Patent:
20190326923, Oct 24, 2019
Filed:
Apr 19, 2019
Appl. No.:
16/389808
Inventors:
- Carlsbad CA, US
Rakesh Kumar Palani - Irvine CA, US
Suman Sah - Colorado Springs CO, US
International Classification:
H03M 1/78
Abstract:
A system (e.g., a transmitter system on chip) comprises a digital-to-analog converter configured to convert an N-bit digital signal to a corresponding analog signal, where N is an integer greater than 1. The digital-to-analog converter may comprise N bias circuits, where each of the bias circuits is configured to generate a bias current, and route the bias current based on a value of a respective one of the N bits of the N-bit digital signal. Each of the N bias circuits may comprises a resistor network and a pair of switching circuits.
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Suman P Sah from Colorado Springs, CO, age ~37 Get Report