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Sylvie Mignot Phones & Addresses

  • Slingerlands, NY
  • Phoenix, AZ
  • Wynantskill, NY
  • Minneapolis, MN

Publications

Us Patents

Via Formation Using Sidewall Image Transfer Process To Define Lateral Dimension

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US Patent:
20160336225, Nov 17, 2016
Filed:
May 13, 2015
Appl. No.:
14/710894
Inventors:
- Armonk NY, US
- Grand Cayman Islands, KY
- Coppell TX, US
Sylvie M. Mignot - Slingerlands NY, US
Yann A. Mignot - Slingerlands NY, US
Hosadurga K. Shobha - Niskayuna NY, US
Terry A. Spooner - Clifton Park NY, US
Wenhui Wang - Clifton Park NY, US
Yongan Xu - Niskayuna NY, US
International Classification:
H01L 21/768
H01L 23/528
H01L 23/535
Abstract:
A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Finfet Device Including A Uniform Silicon Alloy Fin

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US Patent:
20160126353, May 5, 2016
Filed:
Oct 29, 2014
Appl. No.:
14/526617
Inventors:
- Grand Cayman, KY
Jody A. Fronheiser - Delmar NY, US
Yi Qi - Niskayuna NY, US
Sylvie Mignot - Slingerlands NY, US
International Classification:
H01L 29/78
H01L 29/66
H01L 21/225
H01L 21/02
H01L 21/324
H01L 29/165
H01L 29/06
Abstract:
A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Method For Fabricating Microelectronic Devices With Isolation Trenches Partially Formed Under Active Regions

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US Patent:
20150294904, Oct 15, 2015
Filed:
Nov 8, 2012
Appl. No.:
14/441354
Inventors:
- Paris, FR
Sylvie Mignot - Slingerlands NY, US
Romain Wacquez - Marseille, FR
Assignee:
Commissariat a l'energie atomique et aux energies alternatives - Paris
International Classification:
H01L 21/762
H01L 29/06
H01L 21/311
Abstract:
A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
Sylvie M Mignot from Slingerlands, NY, age ~53 Get Report