Tao Wu

8127979, Mar 6, 2012

Sep 25, 2010

12/890662

Tao Wu - Chandler AZ, US
Nicolas R. Watts - Phoenix AZ, US

Intel Corporation - Santa Clara CA

B23K 31/02
C23D 5/02

22818022, 228214, 228215, 205125

Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.

8461036, Jun 11, 2013

Dec 22, 2009

12/645195

Tao Wu - Chandler AZ, US
Reynaldo Alberto Olmedo - Phoenix AZ, US

Intel Corporation - Santa Clara CA

H01L 21/00
H01L 21/44
H01L 23/00
H01R 43/20
H05K 3/10
C25D 5/12

438614, 29842, 29884, 205125, 205181, 257741, 257E21214, 257E2301, 257E23031, 438106, 438666, 438678, 438686

Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate, masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.

8643184, Feb 4, 2014

Oct 31, 2012

13/665741

Zhichao Zhang - Chandler AZ, US
Tolga Memioglu - Chandler AZ, US
Tao Wu - Chandler AZ, US
Kemal Aygun - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 23/48
H01L 23/52
H01L 29/40
H01L 23/04

257758, 257690, 257691, 257698, 257734, 257E23019, 257E23142

Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

20090321932, Dec 31, 2009

Jun 30, 2008

12/217068

Javier Soto Gonzalez - Chandler AZ, US
Tao Wu - Chandler AZ, US
Pallavi Alur - Chandler AZ, US
Mihir Roy - Chandler AZ, US
Sheng Li - Gilbert AZ, US
Reynaldo Olmedo - Phoenix AZ, US

H01L 23/48
H01L 21/4763
H01L 23/52
H01L 21/441
H01L 23/485
H01L 21/44

257750, 438622, 438613, 257766, 257774, 257E21477, 257E23011, 257E23021

A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist layer is removed from the substrate and the substrate is finished for use with a package.

20120077054, Mar 29, 2012

Sep 25, 2010

12/890661

Tao WU - Chandler AZ, US

B32B 15/01
C25D 1/00
B32B 15/04

428600, 428672, 428670, 205 67

Electronic assemblies including coreless substrates having a surface finish, and their manufacture, are described. One method includes electrolytically plating a first copper layer on a metal core in an opening in a patterned photoresist layer. A gold layer is electrolytically plated on the first copper layer in the opening. An electrolytically plated palladium layer is formed on the gold layer. A second copper layer is electrolytically plated on the palladium layer. After the electrolytically plating the second copper layer, the metal core and the first copper layer are removed, wherein a coreless substrate remains. Other embodiments are described and claimed.

20120161330, Jun 28, 2012

Dec 22, 2010

12/975934

Mark S. Hlad - Chandler AZ, US
Islam A. Salama - Chandler AZ, US
Mihir K. Roy - Chandler AZ, US
Tao Wu - Chandler AZ, US
Yueli Liu - Gilbert AZ, US
Kyu Oh Lee - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 23/48
H01L 21/50
H01L 21/52

257774, 438121, 257E23011, 257E215, 257E21499

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

20130081753, Apr 4, 2013

Apr 3, 2012

13/438200

Chin-An Tan - Troy MI, US
Bongsu Kang - Fort Wayne IN, US
Wayne W. Cai - Troy MI, US
Tao Wu - Tempe AZ, US

GM GLOBAL TECHNOLOGY OPERATIONS LLC - Detroit MI

B29C 65/04

156 736, 156350

A vibration welding system includes a controller, welding horn, an anvil, and a passive damping mechanism (PDM). The controller generates an input signal having a calibrated frequency. The horn vibrates in a desirable first direction at the calibrated frequency in response to the input signal to form a weld in a work piece. The PDM is positioned with respect to the system, and substantially damps or attenuates vibration in an undesirable second direction. A method includes connecting the PDM having calibrated properties and a natural frequency to an anvil of an ultrasonic welding system. Then, an input signal is generated using a weld controller. The method includes vibrating a welding horn in a desirable direction in response to the input signal, and passively damping vibration in an undesirable direction using the PDM.

20130285242, Oct 31, 2013

Dec 19, 2011

13/976194

Nicholas R. Watts - Phoenix AZ, US
Tao Wu - Chandler AZ, US

H01L 23/498
H01L 23/488

257738, 257773

An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips.