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Tze Ping Chen

from San Jose, CA
Deceased
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Also known as:
Tze Ping Chentze, Tzeping Ping Chen, Tzeping P Chen, Tzeping K Chen, Ping Chen, Karin P Chen, Peiling Chen, Ping Chen Tzeping
Related to:
Yixin Chen, 52Wenchang Chen, 56Hui Tzu ChenJerry Chen, 47Pichu ChenWen Shan Chen, 53Wen Jung Chen, 58Chen Ping, 39Lucy Q Chen, 53Tze Ping Chentze, 79Hsiuwan Wan Chenhsiu, 77
Connected to:
Adela Chen, 45Aidong Chen, 56Aile Chen, 40Aiqun Chen, 56Aishun Chen, 46Aiting Chen, 39Albertina L Chen, 78Alec C Chen, 61Allison Y Chen, 42Andrea H Chen, 40

Tze Chen Phones & Addresses

  • San Jose, CA
  • 733 Southgate Dr, State College, PA 16801
  • 445 Waupelani Dr, State College, PA 16801
  • 1201 College Ave, State College, PA 16801
  • Santa Clara, CA
  • Salisbury, MD
  • Smyrna, GA

Publications

Us Patents

Electrostatic Discharge Protection Circuit Employing A Micro Electro-Mechanical Systems (Mems) Structure

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US Patent:
7944655, May 17, 2011
Filed:
May 28, 2008
Appl. No.:
12/128108
Inventors:
Tze Wee Chen - Stanford CA, US
William Loh - Fremont CA, US
Choshu Ito - San Mateo CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.

Design Methodology For Preventing Functional Failure Caused By Cdm Esd

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US Patent:
20100100859, Apr 22, 2010
Filed:
Oct 21, 2008
Appl. No.:
12/255002
Inventors:
Choshu Ito - San Mateo CA, US
Tze Wee Chen - Stanford CA, US
William Loh - Fremont CA, US
Assignee:
LSI CORPORATION - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 5
Abstract:
A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.
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Tze Ping Chen from San Jose, CADeceased Get Report