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Sriram R Vangal

from Campbell, CA
Age ~52
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Also known as:
Sriram R Vanjal, Vangal R Sriram, Vangal Spiram
Related to:
Reshma P Gorur, 48
Connected to:
Hemalatha Vangala, 55Kalpana A Vangala, 39Vasavi Vangala, 39Venugopal R Vangala, 49Daniel P Vangalis, 90Zena Vangalloway, 64Bill Vangammeren, 70Darin L Vangammeren, 48Gaynelle R Vangampleare, 95Asha Vangani, 85

Sriram Vangal Phones & Addresses

  • Campbell, CA
  • 3750 Hilton Head Ter, Portland, OR 97229
  • Chandler, AZ
  • 6859 Vinings Way, Hillsboro, OR 97124
  • 2753 Overlook Dr, Hillsboro, OR 97124
  • Aloha, OR
  • Seattle, WA

Work

Company: Intel corporation Nov 1995 Position: Principal research scientist

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Linköping University 2003 to 2007 Specialities: Vlsi Design

Skills

Soc • Microprocessors • Low Power Design • Embedded Systems • Vlsi • Circuit Design • Semiconductors • Silicon • Ic • Power Management • Cmos • Computer Architecture • Asic • Integrated Circuit Design • High Performance Computing • Verilog • Simulations • R&D • Fpga • Digital Signal Processors • Analog Circuit Design • Signal Processing • Research • Formal Verification • Technical Leadership • Application Specific Integrated Circuits • Research and Development

Industries

Semiconductors

Resumes

Resumes

Sriram Vangal Photo 1

Principal Research Scientist

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Principal Research Scientist
Bpl Health Management Solutions Aug 1993 - Dec 1993
Research and Development Engineer
Education:
Linköping University 2003 - 2007
Doctorates, Doctor of Philosophy, Vlsi Design University of Nebraska - Lincoln 1993 - 1995
Master of Science, Masters, Computer Engineering Pg Center, Kolar 1989 - 1993
Bachelor of Engineering, Bachelors, Electronics Engineering
Skills:
Soc
Microprocessors
Low Power Design
Embedded Systems
Vlsi
Circuit Design
Semiconductors
Silicon
Ic
Power Management
Cmos
Computer Architecture
Asic
Integrated Circuit Design
High Performance Computing
Verilog
Simulations
R&D
Fpga
Digital Signal Processors
Analog Circuit Design
Signal Processing
Research
Formal Verification
Technical Leadership
Application Specific Integrated Circuits
Research and Development

Publications

Us Patents

Flip Flop Circuit

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US Patent:
6459316, Oct 1, 2002
Filed:
Dec 8, 2000
Appl. No.:
09/733216
Inventors:
Sriram R. Vangal - Hillsboro OR
Dinesh Somasekhar - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 3289
US Classification:
327202, 327203, 326 95, 326 96
Abstract:
A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

Storage Element With Stock Node Capacitive Load

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US Patent:
6483363, Nov 19, 2002
Filed:
Sep 15, 2000
Appl. No.:
09/663749
Inventors:
Tanay Karnik - Portland OR
Sriram R. Vangal - Hillsboro OR
Venkat S. Veeramachaneni - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 3356
US Classification:
327211, 327210
Abstract:
A storage element includes a forward inverter and a feedback inverter cross-coupled between a storage node and a feedback node. A capacitive load within the feedback inverter is coupled to the storage node when the storage element holds data and is not coupled to the storage node when the storage element is loading. The capacitive load reduces the storage elements susceptibility to soft errors when holding data, and does not appreciably slow the storage element when data is loading. The capacitive load is implemented using the gate capacitance of complementary transistors connected to stack nodes within the feedback inverter. A flip-flop includes cascaded latches, one or more of which have the internal capacitance.

Storage Element With Switched Capacitor

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US Patent:
6504412, Jan 7, 2003
Filed:
Sep 15, 2000
Appl. No.:
09/663750
Inventors:
Sriram R. Vangal - Hillsboro OR
Tanay Karnik - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 764
US Classification:
327203, 327337, 327210, 327212, 327218
Abstract:
A latch includes a pair of inverters cross-coupled between a storage node and a feedback node. A capacitor is conditionally coupled to the feedback node through a pass gate such that the capacitor is coupled to the feedback node when the latch holds data and is not coupled to the feedback node when the latch is loading. The capacitor reduces the latchs susceptibility to soft errors when holding data, and does not appreciably slow the latch when data is loading. The capacitor is implemented using the gate capacitance of complementary transistors. A flip-flop includes cascaded latches, one or more of which have a switched capacitor on a feedback node.

Integrated Circuit Interconnect Routing Using Double Pumped Circuitry

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US Patent:
6535045, Mar 18, 2003
Filed:
Jul 9, 1998
Appl. No.:
09/112466
Inventors:
Sriram R. Vangal - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03L 500
US Classification:
327333, 327163, 375375
Abstract:
Internal integrated circuit interconnect communication circuitry dual edge triggered latching circuits to transmit two data signals over a common interconnect line during one clock cycle. That is, one data bit is transmitted during each phase of a system clock over a common interconnect line. The latching circuits can be flip-flop circuits. An optional repeater circuit has dual edge triggered flip-flop circuits for repeating the common interconnect line signal on a second common interconnect line. A dual edge triggered latching receiver circuit splits, or decodes, the two combined incoming data signals into separate outgoing data signals.

Flip Flop Circuit

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US Patent:
6597223, Jul 22, 2003
Filed:
Jul 30, 2002
Appl. No.:
10/208130
Inventors:
Sriram R. Vangal - Hillsboro OR
Dinesh Somasekhar - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 3289
US Classification:
327202, 327203, 326 95, 326 96
Abstract:
A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

Pipelined Compressor Circuit

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US Patent:
6701339, Mar 2, 2004
Filed:
Dec 8, 2000
Appl. No.:
09/733482
Inventors:
Sriram R. Vangal - Hillsboro OR
Dinesh Somasekhar - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 752
US Classification:
708709
Abstract:
A pipelined four-to-two compressor includes sequential elements with embedded logic. One sequential element is a flip flop with complementary outputs that includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. Keeper nodes can also be dynamic flip flop outputs that pre-charge each clock cycle. Another flip flop with embedded logic receives the dynamic output, applies further logic, and provides a static output.

Weak Current Generation

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US Patent:
6735131, May 11, 2004
Filed:
Jan 7, 2002
Appl. No.:
10/041855
Inventors:
Sriram R. Vangal - Aloha OR
Assignee:
Intel Corporation - Santa Monica CA
International Classification:
G11C 700
US Classification:
365201, 36518905, 36518912
Abstract:
Electronic elements that include a weak current source are configured to enable different selected levels of weak current to be delivered to a circuit. A control input is connected to the electronic element to receive control signals that specify a selected level of weak current. The identities and the timing of the control signals are determined by signals delivered through a scan register.

Integrated Circuit Interconnect Routing Using Double Pumped Circuitry

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US Patent:
6791376, Sep 14, 2004
Filed:
Dec 4, 2002
Appl. No.:
10/309558
Inventors:
Sriram R. Vangal - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 1700
US Classification:
327 99, 327355
Abstract:
Circuit interconnect communication circuitry dual edge triggered latching circuits transmit two data signals over a common interconnect line during one clock cycle; on signal is transmitted during each phase of a system clock over the common interconnect line. The latching circuits may be flip-flop circuits. A repeater circuit may have dual edge triggered flip-flop circuits for repeating the common interconnect line signal on a second common interconnect line. A receiver, including dual edge triggered latching circuitry, decodes the combined incoming data signals into separate outgoing data signals.
Control profile
Sriram R Vangal from Campbell, CA, age ~52 Get Report