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Vincent E Vonbokern

from Rescue, CA
Age ~53

Vincent Vonbokern Phones & Addresses

  • 3500 Lapis Ct, Rescue, CA 95672
  • Rancho Cordova, CA
  • Alameda, CA
  • Silver Spring, MD
  • Blacksburg, VA
  • Folsom, CA

Publications

Us Patents

Method And Apparatus To Control Device Temperature

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US Patent:
6470238, Oct 22, 2002
Filed:
Jun 17, 1999
Appl. No.:
09/335101
Inventors:
Puthiya K. Nizar - El Dorado Hills CA
David J. McDonnell - Fair Oaks CA
Brian K. Langendorf - El Dorado Hills CA
Michael G. LaTondre - Fair Oaks CA
Jeff L. Rabe - Gold River CA
Tom A. Sutera - Folsom CA
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05D 2300
US Classification:
700299, 700153, 702130
Abstract:
A method for controlling device temperature. The method involves determining access rate to a component, comparing the access rate with a predetermined threshold modified by a weighted value and controlling the temperature of the component through corrective action.

Accelerated Graphics Port Expedite Cycle Throttling Control Mechanism

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US Patent:
6784890, Aug 31, 2004
Filed:
Mar 2, 1998
Appl. No.:
09/033529
Inventors:
Brian L. Bergeson - Folsom CA
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1318
US Classification:
345535, 345503, 345520, 345531, 711150, 711151, 710241
Abstract:
A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

Method And Apparatus To Control Core Logic Temperature

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US Patent:
59536853, Sep 14, 1999
Filed:
Nov 26, 1997
Appl. No.:
8/979835
Inventors:
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05D 2300
US Classification:
702136
Abstract:
A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

Abort Of Dram Read Ahead When Pci Read Multiple Has Ended

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US Patent:
63144727, Nov 6, 2001
Filed:
Dec 1, 1998
Appl. No.:
9/203127
Inventors:
Tuong P. Trieu - Folsom CA
David D. Lent - Placerville CA
Ashish S. Gadagkar - Folsom CA
Vincent E. VonBokern - Rescue CA
Zohar Bogin - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 300
G06F 1200
G06F 1214
G06F 1300
US Classification:
710 5
Abstract:
A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

Method And Apparatus To Control Core Logic Temperature

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US Patent:
61732176, Jan 9, 2001
Filed:
Dec 15, 1997
Appl. No.:
8/990711
Inventors:
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05D 2300
US Classification:
700299
Abstract:
A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

Selective Automatic Precharge Of Dynamic Random Access Memory Banks

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US Patent:
61816191, Jan 30, 2001
Filed:
Dec 4, 1998
Appl. No.:
9/205508
Inventors:
Zohar Bogin - Folsom CA
Vincent VonBokern - Rescue CA
David Freker - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
365203
Abstract:
A method and apparatus for selective automatic precharge of dynamic random access memory banks is disclosed. By automatically precharging memory banks under certain conditions overall memory throughput can be improved because precharging is performed on a more selective basis. In one embodiment, the present invention provides support for multiple open banks of memory within a single memory sub-system. When multiple banks of memory are open simultaneously, a bank of memory that is less likely to be accessed in the future can be precharged when a new bank of memory is to be opened to service a memory request.

Apparatus And Method For Preventing Access To Smram Space Through Agp Addressing

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US Patent:
61924555, Feb 20, 2001
Filed:
Mar 30, 1998
Appl. No.:
9/050627
Inventors:
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711154
Abstract:
A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and re-directs the access to non-SMRAM space if the access is directed to the SMRAM space.

Method And Apparatus For Propagating A Signal Between Synchronous Clock Domains Operating At A Non-Integer Frequency Ratio

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US Patent:
59616490, Oct 5, 1999
Filed:
Dec 4, 1997
Appl. No.:
8/985391
Inventors:
Narendra Khandekar - Folsom CA
Ashish S. Gadagkar - Sunnyvale CA
Robert F. Kubick - El Dorado Hills CA
Vincent E. VonBokern - Rescue CA
Manish Muthal - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 172
US Classification:
713400
Abstract:
A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.
Vincent E Vonbokern from Rescue, CA, age ~53 Get Report