Vincent E Vonbokern

6470238, Oct 22, 2002

Jun 17, 1999

09/335101

Puthiya K. Nizar - El Dorado Hills CA
David J. McDonnell - Fair Oaks CA
Brian K. Langendorf - El Dorado Hills CA
Michael G. LaTondre - Fair Oaks CA
Jeff L. Rabe - Gold River CA
Tom A. Sutera - Folsom CA
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA

Intel Corporation - Santa Clara CA

G05D 2300

700299, 700153, 702130

A method for controlling device temperature. The method involves determining access rate to a component, comparing the access rate with a predetermined threshold modified by a weighted value and controlling the temperature of the component through corrective action.

6784890, Aug 31, 2004

Mar 2, 1998

09/033529

Brian L. Bergeson - Folsom CA
Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA

Intel Corporation - Santa Clara CA

G06F 1318

345535, 345503, 345520, 345531, 711150, 711151, 710241

A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

59536853, Sep 14, 1999

Nov 26, 1997

8/979835

Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA

Intel Corporation - Santa Clara CA

G05D 2300

702136

A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

63144727, Nov 6, 2001

Dec 1, 1998

9/203127

Tuong P. Trieu - Folsom CA
David D. Lent - Placerville CA
Ashish S. Gadagkar - Folsom CA
Vincent E. VonBokern - Rescue CA
Zohar Bogin - Folsom CA

Intel Corporation - Santa Clara CA

G06F 300
G06F 1200
G06F 1214
G06F 1300

710 5

A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

61732176, Jan 9, 2001

Dec 15, 1997

8/990711

Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA

Intel Corporation - Santa Clara CA

G05D 2300

700299

A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

61816191, Jan 30, 2001

Dec 4, 1998

9/205508

Zohar Bogin - Folsom CA
Vincent VonBokern - Rescue CA
David Freker - Folsom CA

Intel Corporation - Santa Clara CA

G11C 700

365203

A method and apparatus for selective automatic precharge of dynamic random access memory banks is disclosed. By automatically precharging memory banks under certain conditions overall memory throughput can be improved because precharging is performed on a more selective basis. In one embodiment, the present invention provides support for multiple open banks of memory within a single memory sub-system. When multiple banks of memory are open simultaneously, a bank of memory that is less likely to be accessed in the future can be precharged when a new bank of memory is to be opened to service a memory request.

61924555, Feb 20, 2001

Mar 30, 1998

9/050627

Zohar Bogin - Folsom CA
Vincent E. VonBokern - Rescue CA

Intel Corporation - Santa Clara CA

G06F 1200

711154

A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and re-directs the access to non-SMRAM space if the access is directed to the SMRAM space.

59616490, Oct 5, 1999

Dec 4, 1997

8/985391

Narendra Khandekar - Folsom CA
Ashish S. Gadagkar - Sunnyvale CA
Robert F. Kubick - El Dorado Hills CA
Vincent E. VonBokern - Rescue CA
Manish Muthal - Folsom CA

Intel Corporation - Santa Clara CA

G06F 172

713400

A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.