Vladimir M Pentkovski

6356270, Mar 12, 2002

Mar 31, 1998

09/053231

Vladimir Pentkovski - Folsom CA
Hsien-Cheng E. Hsieh - Gold River CA
Hsien-Hsin Lee - El Dorado Hills CA
Subramaniam Maiyuran - Fair Oaks CA

Intel Corporation - Santa Clara CA

G06T 160

345530, 345557, 711118

The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

6369813, Apr 9, 2002

Jun 30, 1998

09/109257

Vladimir Pentkovski - Folsom CA
Deep Buch - Folsom CA
Michael K. Dwyer - El Dorado Hills CA
Hsien-Hsin Lee - El Dorado Hills CA
Hsien-Cheng E. Hsieh - Gold River CA

Intel Corporation - Santa Clara CA

G06T 1500

345419, 345537

The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M vertex coordinates corresponding entirely to the N polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.

6377970, Apr 23, 2002

Mar 31, 1998

09/052904

Mohammad A. Abdallah - Folsom CA
Vladimir Pentkovski - Folsom CA

Intel Corporation - Santa Clara CA

G06F 752

708603, 712 22

A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

6466217, Oct 15, 2002

Dec 22, 1999

09/470924

Hsien-cheng Emile Hsieh - Gold River CA
Vladimir M. Pentkovski - Folsom CA

Intel Corporation - Santa Clara CA

G06F 120

345503, 345501, 345502, 345522

A method and apparatus of rendering an image is disclosed. In one embodiment, a graphic system has a switch detector, which detects a switch condition in the graphics system. The graphics system also has a rendering block, which renders a plurality of layers according to the detected switch condition.

6480868, Nov 12, 2002

Apr 27, 2001

09/844728

Mohammad A.F. Abdallah - Folson CA
Hsien-Cheng E. Hsieh - Gold River CA
Thomas R. Huff - Portland OR
Vladimir Pentkovski - Folsom CA
Patrice Roussel - Portland OR
Shreekant S. Thakkar - Portland OR

Intel Corporation - Santa Clara CA

G06F 7100

708204, 712221

A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

6502115, Dec 31, 2002

Apr 27, 2001

09/845610

Mohammad A. F. Abdallah - Folsom CA
Hsien-Cheng E. Hsieh - Gold River CA
Thomas R. Huff - Portland OR
Vladimir Pentkovski - Folsom CA
Patrice Roussel - Portland OR
Shreekant S. Thakkar - Portland OR

Intel Corporation - Santa Clara CA

G06F 700

708204, 712220

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

6584547, Jun 24, 2003

Mar 9, 2001

09/803357

Salvador Palanca - Folsom CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Vladimir Pentkovski - Folsom CA
Steve Tsai - Rancho Cordova CA

Intel Corporation - Santa Clara CA

G06F 1200

711133, 711136, 711128, 711145, 711144, 711154, 711155, 711156

A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

6643745, Nov 4, 2003

Mar 31, 1998

09/053383

Salvador Palanca - Folsom CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Vladimir Pentkovski - Folsom CA
Steve Tsai - Rancho Cordova CA
Subramaniam Maiyuran - Fair Oaks CA
Jagannath Keshava - Folsom CA
Hsien-Hsin Lee - El Dorado Hills CA
Steve Spangler - El Dorado Hills CA
Suresh Kuttuva - Folsom CA
Praveen Mosur - Folsom CA

Intel Corporation - Santa Clara CA

G06F 1200

711138, 711137

A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.