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Walid Mohamed Elgharbawy

from San Jose, CA
Age ~49
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Also known as:
Walid M Elgharbawy
Related to:
Mohamed W Elgharbawy, 24
Connected to:
Johanna S Elgharbi, 55Shewekar Elgharably, 74Lewa Elghariani, 43Elias I Elghazal, 58Sami Y Elghazawi, 52Latifa Elghissassi, 70Ahmed M Elghoraiby, 63Janina Elghor, 65Ahmed Elghory, 33Adam I Elghoul, 39

Walid Elgharbawy Phones & Addresses

  • San Jose, CA
  • Cupertino, CA
  • Santa Clara, CA
  • 15868 W West Union Rd, Portland, OR 97229
  • 200 E Lewis St, Lafayette, LA 70503

Work

Company: Altera May 2013 Position: Senior member of technical staff

Education

Degree: PhD School / High School: University of Louisiana at Lafayette 2002 to 2005 Specialities: Computer Engnieering

Skills

Asic • Verilog • Vlsi • Eda • Tcl • Perl • Computer Architecture • Embedded Systems • Algorithms • Debugging • Linux • Vhdl • Static Timing Analysis • Spice • Simulations • Microprocessors • Processors • Hardware Architecture • Circuit Design • Logic Design • Soc • Rtl Design • Application Specific Integrated Circuits • System on A Chip

Languages

English • Arabic

Interests

Civil Rights and Social Action • Education • Poverty Alleviation • Science and Technology • Human Rights

Industries

Computer Hardware

Resumes

Resumes

Walid Elgharbawy Photo 1

Senior Soc Design Engineer

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Location:
19014 Tilson Ave, Cupertino, CA 95014
Industry:
Computer Hardware
Work:
Altera since May 2013
Senior Member Of Technical Staff
Oracle Feb 2010 - May 2013
Principal Engineer
Sun Microsystems Dec 2006 - Feb 2010
Member of Technical Staff (MTS)
Intel Dec 2005 - Oct 2006
Senior Product Development Engineer
University of Louisiana at Lafayette Jan 2001 - Dec 2005
Lecturer / Research Assistant
Education:
University of Louisiana at Lafayette 2002 - 2005
PhD, Computer Engnieering University of Louisiana at Lafayette 2001 - 2002
MSc, Computer Engnieering Cairo University 1992 - 1997
B.Sc., Electronics and Communication Engineering
Skills:
Asic
Verilog
Vlsi
Eda
Tcl
Perl
Computer Architecture
Embedded Systems
Algorithms
Debugging
Linux
Vhdl
Static Timing Analysis
Spice
Simulations
Microprocessors
Processors
Hardware Architecture
Circuit Design
Logic Design
Soc
Rtl Design
Application Specific Integrated Circuits
System on A Chip
Interests:
Civil Rights and Social Action
Education
Poverty Alleviation
Science and Technology
Human Rights
Languages:
English
Arabic

Publications

Us Patents

Dynamic Threshold P-Channel Mosfet For Ultra-Low Voltage Ultra-Low Power Applications

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US Patent:
20070267702, Nov 22, 2007
Filed:
May 11, 2007
Appl. No.:
11/801919
Inventors:
Walid Elgharbawy - Lafayette LA, US
Magdy Bayoumi - Lafayette LA, US
International Classification:
H01L 29/76
US Classification:
257365000
Abstract:
A dynamic threshold voltage p-channel MOSFET (PMOS) for ultra-low power ultra-low voltage applications is disclosed. These applications are of low-to-moderate performance requirements; hence ultra-low voltage subthreshold operation, where the supply voltage is less than the transistors threshold voltage, is suitable. By tying the PMOS body to the output node of the transistor circuit in which this PMOS is part of will provide the necessary body bias for this PMOS threshold voltage to change dynamically with the circuit's output status. The dynamic change of the PMOS transistor threshold voltage will consequently dynamically increase or decrease the subthreshold leakage current which is the switching current in subthreshold circuits.
Control profile
Walid Mohamed Elgharbawy from San Jose, CA, age ~49 Get Report