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Warren E Maule

from Iola, TX
Age ~67
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Also known as:
Edward Maule Warren, Warren E Manule, Warren E Mauk, Wade Maule, William Maule
Related to:
Tai Athay, 44Mark S Handt, 63Kenneth E BensonGermaine K Benson, 94Anita T Torres, 69Grayson W Haule, 62Laura J MauleMary Maule, 32Brian Maule, 28Renee L Maule, 64
Connected to:
Amanda M Maule, 43Billie J Maule, 42Colleen M Maule, 27Cruz Maule, 33Dylan Maule, 31Ellen Maule, 66Rosanna Maule, 62Shondra Maule, 51Theresa Maule, 58Richard Maulen, 63

Warren Maule Phones & Addresses

  • Iola, TX
  • Bryan, TX
  • Flushing, NY
  • 8359 Boca Glades Blvd E, Boca Raton, FL 33434
  • 12131 Taku Rd, Cedar Park, TX 78613 (512) 259-2824
  • 2701 Taku Rd, Cedar Park, TX 78613 (512) 259-2824
  • Staten Island, NY
  • Boynton Beach, FL
  • Austin, TX
  • Davie, FL
  • 2701 Taku Rd, Cedar Park, TX 78613 (512) 963-8006

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

w***[email protected]

Publications

Us Patents

Error Recovery Mechanism For A High-Performance Interconnect

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US Patent:
6487679, Nov 26, 2002
Filed:
Nov 9, 1999
Appl. No.:
09/437041
Inventors:
Ravi Kumar Arimilli - Austin TX
Vicente Enrique Chung - Austin TX
Warren Edward Maule - Cedar Park TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1108
US Classification:
714 17, 714 43
Abstract:
An error recovery mechanism for an interconnect is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. In response to a parity error occurring on the bus, the bus slave issues a bus parity error response to the bus master via the bus. After waiting for a predetermined number of bus cycles to allow the bus to idle, the bus master then issues a RESTART bus command packet to the bus slave via the bus to clear the parity error. If the RESTART bus command packet is received correctly, the slave bus will remove the parity error response such that normal bus communication may resume.

Method And Apparatus For High Performance Transmission Of Ordered Packets On A Bus Within A Data Processing System

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US Patent:
6581116, Jun 17, 2003
Filed:
Nov 9, 1999
Appl. No.:
09/437042
Inventors:
Ravi Kumar Arimilli - Austin TX
Vicente Enrique Chung - Austin TX
Warren Edward Maule - Cedar Park TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
710110, 710 7, 710 29, 710 36, 710107
Abstract:
A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus master consecutively issues multiple packets, such as command packets, to the bus slave on the bus. The packets include order sensitive packets and non-order sensitive packets. In response to a temporary inability of the bus slave to process a particular one of the order sensitive packets due to a lack of resources, the bus slave keeps retrying the particular order sensitive packet. When resources become available, the bus slave processes the retried order sensitive packets in order while allowing the retried non-order sensitive packets to be processed in any order.

Sequencing Data On A Shared Data Bus Via A Memory Buffer To Prevent Data Overlap During Multiple Memory Read Operations

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US Patent:
6622222, Sep 16, 2003
Filed:
Apr 26, 2001
Appl. No.:
09/843071
Inventors:
Ravi Kumar Arimilli - Austin TX
Warren Edward Maule - Cedar Park TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
711154, 710 52, 710 58, 711151, 711158, 711147
Abstract:
Disclosed is a method and memory subsystem that allows for speculative issuance of reads to a DRAM array to provide efficient utilization of the data out bus and faster read response for accesses to a single DRAM array. Two read requests are issued simultaneously to a first and second DRAM in the memory subsystem, respectively. Data issued from the first DRAM is immediately placed on the data out bus, while data issued from the second DRAM is held in an associated buffer. The processor or memory controller then generates a release signal if the second read is not speculative or is correctly speculated. The release signal is sent to the second DRAM after the first issued data is placed on the bus. The release signal releases the data held in the buffer associated with the second DRAM from the buffer to the data out bus. Because the data has already been issued when the release signal is received, no loss of time is incurred in issuing the data from the DRAM and only a small clock cycle delay occurs between the first issued data and the second issued data on the data out bus.

Dram With Memory Independent Burst Lengths For Reads Versus Writes

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US Patent:
6675270, Jan 6, 2004
Filed:
Apr 26, 2001
Appl. No.:
09/843060
Inventors:
Ravi Kumar Arimilli - Austin TX
Warren Edward Maule - Cedar Park TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
711155, 711142, 711143, 711156
Abstract:
A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i. e. , a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.

Method And System For Supplier-Based Memory Speculation In A Memory Subsystem Of A Data Processing System

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US Patent:
7130967, Oct 31, 2006
Filed:
Dec 10, 2003
Appl. No.:
10/733948
Inventors:
Ravi Kumar Arimilli - Austin TX, US
Sanjeev Ghai - Round Rock TX, US
Warren Edward Maule - Cedar Park TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711137, 711 5, 711163, 711154
Abstract:
A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller directs an access to a selected row in the system memory to service the memory access request. The memory controller speculatively directs that the selected row will continue to be energized following the access based upon the historical information in the memory speculation table, so that access latency of an immediately subsequent memory access is reduced.

System, Method And Storage Medium For Providing Data Caching And Data Compression In A Memory Subsystem

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US Patent:
7277988, Oct 2, 2007
Filed:
Oct 29, 2004
Appl. No.:
10/977846
Inventors:
Kevin C. Gower - LaGrangeville NY, US
Mark W. Kellogg - Henrietta NY, US
Warren E. Maule - Cedar Park TX, US
Robert B. Tremaine - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711118, 711119, 710100, 710305
Abstract:
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

System, Method And Storage Medium For Providing A Serialized Memory Interface With A Bus Repeater

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US Patent:
7296129, Nov 13, 2007
Filed:
Jul 30, 2004
Appl. No.:
10/903178
Inventors:
Kevin C. Gower - LaGrangeville NY, US
Kevin W. Kark - Poughkeepsie NY, US
Mark W. Kellogg - Henrietta NY, US
Warren E. Maule - Cedar Park TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
G06F 13/00
G11C 5/06
US Classification:
711167, 711115, 711154, 711156, 711157, 711170, 711101, 710100, 710313, 365 63
Abstract:
A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

System, Method And Storage Medium For A Memory Subsystem Command Interface

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US Patent:
7299313, Nov 20, 2007
Filed:
Oct 29, 2004
Appl. No.:
10/977793
Inventors:
Kevin C. Gower - LaGrangeville NY, US
Warren E. Maule - Cedar Park TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711100, 711167, 710 24, 710 30, 710105
Abstract:
A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
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Warren E Maule from Iola, TX, age ~67 Get Report