Hong X Zhao

6721929, Apr 13, 2004

May 11, 2001

09/854146

Jun Li - San Jose CA
Hong Zhao - Fremont CA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 6, 716 4, 716 5

A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (âRCâ) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.

7073140, Jul 4, 2006

Aug 29, 2003

10/651617

Jun Li - San Jose CA, US
Athanasius Spyrou - Sunnyvale CA, US
Hong Zhao - Fremont CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/90

716 4

Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

7310792, Dec 18, 2007

Dec 15, 2004

11/014096

Nishath K. Verghese - Sunnyvale CA, US
Hong Zhao - Fremont CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716 6, 716 4, 716 5

A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit parameter values. This delay equation calculates the delay for any value in the circuit parameter range. Similar methodology is used to model simultaneous variation of two circuit parameters. The cell is characterized at just six circuit parameter pairs to interpolate the delay equation for any circuit parameter pair in the characterized ranges. This methodology can be extended to accommodate variation of multiple circuit parameters using similar interpolation techniques.

7549134, Jun 16, 2009

Jun 30, 2006

11/479279

Jun Li - San Jose CA, US
Athanasius Spyrou - Sunnyvale CA, US
Hong Zhao - Fremont CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716 5, 716 4, 716 6

Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

20210239879, Aug 5, 2021

Dec 15, 2020

17/247528

- Spring TX, US
Junzhe Sun - San Jose CA, US
Carey M. Marcinkovich - The Woodlands TX, US
Hong Zhao - Houston TX, US
Erik R. Neumann - Houston TX, US

G01V 99/00
G06F 30/20
G06F 17/18

A method for partitioning a search direction when using least squares reverse time migration (LSRTM) is provided. LSRTM may be used iteratively in order to improve imaging accuracy. As part of LSRTM, multiple local line searches may be performed. In particular, image space may be partitioned, such as by using a set of masks. The search direction, such as the gradient, may be partitioned using the set of masks. Local line searches may be performed for each partition of the search direction, resulting in finding respective line search constants. The respective line search constants may then be used for iterating the model in order to improve imaging accuracy.

20190345621, Nov 14, 2019

Jul 26, 2019

16/523929

- Moss Landing CA, US
Ryan J. Gilliam - San Jose CA, US
Hong Zhao - Marina CA, US

C25B 9/04
B23K 20/08
C25B 9/18
C25B 9/08
C25B 13/04
C25B 1/46
C25B 11/02
B23K 26/34

Provided herein are anode assembly, conductive contact strips, electrochemical cells containing the anode assembly and the conductive contact strips, and methods to use and manufacture the same, where the anode assembly includes a plurality of V-shaped, U-shaped, or Z-shaped elements positioned outside the anode shell and in electrical contact with the anode.

20170342576, Nov 30, 2017

May 25, 2017

15/605844

- Moss Landing CA, US
Ryan J. Gilliam - San Jose CA, US
Hong Zhao - Marina CA, US

C25B 9/04
B23K 26/34
C25B 9/18
C25B 9/08
C25B 13/04
C25B 11/02
B23K 20/08
C25B 1/46
B23K 103/14
B23K 101/38
B23K 103/12
B23K 103/16

Provided herein are anode assembly, conductive contact strips, electrochemical cells containing the anode assembly and the conductive contact strips, and methods to use and manufacture the same, where the anode assembly includes a plurality of V-shaped, U-shaped, or Z-shaped elements positioned outside the anode shell and in electrical contact with the anode.

20170250428, Aug 31, 2017

Feb 24, 2017

15/441704

- Moss Landing CA, US
Thomas A. Albrecht - Sunnyvale CA, US
Hong Zhao - Marina CA, US
Diego Martinez - Monterey CA, US
Rebecca L. King - Capitola CA, US

H01M 8/04992
H01M 8/04313
H01M 8/04791

Disclosed herein are methods and systems that relate to an on-line monitoring of a process/system by controlling rate of oxidation of metal ions at an anode in an anode electrolyte of an electrochemical process and controlling rate of reduction of the metal ions in a catalysis process to achieve steady state.