Viktor I Koldiaev

8189376, May 29, 2012

Feb 2, 2009

12/363841

Viktor Koldiaev - San Jose CA, US

Micron Technology, Inc. - Boise ID

G11C 11/34
H01L 27/12

365174, 438149, 365 72, 257347

An integrated circuit device (e. g. , a logic or memory device) having a memory section including a plurality of memory cells, wherein each memory cell thereof includes at least one n-channel transistor having a gate, gate dielectric and first, second and body regions, wherein the gate of the at least one n-channel transistor of each memory cell includes one or more gate materials, disposed on or over the gate dielectric material. The one or more gate materials may include a semiconductor material having one or more acceptor-type doping species disposed therein. The integrated circuit device may further include a logic section including at least one n-channel transistor having a gate, gate dielectric and first, second and body regions, wherein the gate of the n-channel transistor of the logic section may include a gate semiconductor material disposed on or over the gate dielectric material.

8537610, Sep 17, 2013

Jul 12, 2010

12/834418

Serguei Okhonin - Lausanne, CH
Viktor I Koldiaev - Morgan Hill CA, US
Mikhail Nagoga - Pully, CH
Yogesh Luthra - Chavannes-pres-Renens, CH

Micron Technology, Inc. - Boise ID

G11C 16/04
G11C 11/24
H01L 29/788

36518501, 365149, 365150, 3651851, 257316, 257E21646, 257E27084

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

20050040479, Feb 24, 2005

Aug 20, 2003

10/644633

Viktor Koldiaev - San Jose CA, US
George Cheroff - Oakland CA, US

H01L029/76
H01L031/062

257411000, 257412000, 257900000

A spacer () for a MOSFET is provided with an Oxide-Nitride-Oxide structure. The nitride layer () has a structure formed through a process that isolates first oxide layer () from ammonium precursors that may be used to form nitride layer ().

20050255684, Nov 17, 2005

May 17, 2004

10/847538

Viktor Koldiaev - San Jose CA, US
Jeff Babock - Sunnyvale CA, US
George Cheroff - Oakland CA, US

H01L021/425

438528000

A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations within the gate stack to create stable silicon-deuterium bond terminations at the Si—SiOinterface within the gate-channel region. The deuterium is encapsulated in the MOSFET by the use of a Silicon Nitride (SiN) barrier mask. The ability of deuterium to passivate dangling silicon bonds is maximized by removing hydrogen present in the MOSFET and by use of an absorption layer to create a deuterium rich region.

20090200635, Aug 13, 2009

Feb 10, 2009

12/368333

Viktor Koldiaev - San Jose CA, US

H01L 29/06
H01L 21/762
H01L 21/31

257506, 438424, 438761, 257E21546, 257E2902, 257E2124

An integrated circuit device (e.g., a logic or memory device) having a plurality of memory cells each including at least one transistor, wherein transistors of neighboring memory cells are separated by isolation regions. The isolation regions include a first liner layer, a barrier layer disposed on or over the first liner layer, wherein the barrier layer is less than 3 nanometers, and preferably between about 1 nanometer to about 2 nanometers in thickness. The isolation regions further include a second liner layer (comprising, e.g., a silicon nitride material), disposed on or over the barrier layer, and an electrical isolation material, disposed on or over the second liner layer. The barrier layer prohibits, minimizes, reduces, inhibits and/or retards diffusion of nitrogen atoms there through. Also disclosed are methods of manufacturing such integrated circuit devices as well as methods of manufacture of a mask for use in fabrication of integrated circuits, wherein the mask comprises depositing a pad layer, depositing a barrier layer on or over the pad layer wherein the barrier layer includes a thickness of about 1 nanometer to about 2 nanometers, and depositing a hard mask layer on or over the barrier layer which includes a silicon nitride material. The barrier layer prohibits, minimizes, reduces, inhibits and/or retards diffusion of nitrogen atoms there through.

20100259964, Oct 14, 2010

Mar 31, 2010

12/751245

Michael A. Van Buskirk - Saratoga CA, US
Christian Caillat - Versonnex, FR
Viktor I. Koldiaev - Morgan Hill CA, US
Jungtae Kwon - San Jose CA, US
Pierre C. Fazan - Lonay, CH

Innovative Silicon ISi SA - Lausanne

G11C 5/06

365 63

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

20130250699, Sep 26, 2013

May 21, 2013

13/899177

Viktor I. KOLDIAEV - Morgan Hill CA, US
Mikhail NAGOGA - Pully, CH
Yogesh LUTHRA - Chavannes-pres-Renes, CH

MICRON TECHNOLOGY, INC. - Boise ID

H01L 29/78
G11C 16/10
H01L 29/66

36518527, 257314, 438151

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

20140349450, Nov 27, 2014

Aug 13, 2014

14/458569

- Boise ID, US
Viktor KOLDIAEV - Morgan Hill CA, US
Mikhail NAGOGA - Pully, CH
Yogesh LUTHRA - Chavannes-Pres-Renens, CH

MICRON TECHNOLOGY, INC. - Boise ID

H01L 27/108
H01L 21/768
H01L 21/8234

438197

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.