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Rimma A Pirogova

from San Jose, CA
Age ~76
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Also known as:
Rimma P Koldiaev, Rimma V
Phone and address:
430 Navaro Pl UNIT 115, San Jose, CA 95134
Related to:
Viktor I Koldiaev, 74
Connected to:
Alex J Pirogovsky, 53Joshua D Pirogowicz, 46Elizabeth N Pirok, 35Jane E Pirok, 66Lynne P Pirok, 57Arthur J Piroli, 88Rina Piroli, 65Teuta Piroli, 53Alec Pirolli, 39Allison A Pirolli, 39

Rimma Pirogova Phones & Addresses

  • 430 Navaro Pl UNIT 115, San Jose, CA 95134
  • 435 E Central Ave, Morgan Hill, CA 95037
  • Santa Clara, CA

Work

Company: Finscale Jun 2014 Position: Chief engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Novosibirsk State Technical University 1989 Specialities: Electrical Engineering, Philosophy

Skills

Engineers • Fab • Integration

Resumes

Resumes

Rimma Pirogova Photo 1

Chief Engineer

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Location:
1200 Ranchero Way, San Jose, CA 95117
Work:
Finscale
Chief Engineer
Siprosys 2004 - 2011
Research Scientist
Silterra Usa May 2008 - Oct 2008
Research Scientist
Cadence Design Systems Jan 2003 - Dec 2003
Consultant
Interuniversity Microelectronic Center 1998 - 1999
Visiting Researcher
Education:
Novosibirsk State Technical University 1989
Doctorates, Doctor of Philosophy, Electrical Engineering, Philosophy Novosibirsk State Technical University 1966 - 1971
Master of Science, Masters, Physics, Engineering
Skills:
Engineers
Fab
Integration

Publications

Us Patents

Non-Contact Method And Apparatus For On-Line Interconnect Characterization In Vlsi Circuits

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US Patent:
7088121, Aug 8, 2006
Filed:
Nov 17, 2003
Appl. No.:
10/715263
Inventors:
Narain D. Arora - San Jose CA, US
Rimma A. Pirogova - San Jose CA, US
Assignee:
Siprosys, Inc. - San Jose CA
International Classification:
G01R 31/26
US Classification:
324765, 324719, 3241581
Abstract:
A system that facilitates non-invasive in-line characterization of parameters of VLSI circuit interconnects is provided. A plurality of micro-electro-mechanical system (MEMS) cantilevers apply voltage(s) to VLSI circuit interconnect(s) without physical contact thereto. A measuring component measures deflection characteristics of the cantilevers, the deflection(s) correspond to electrical forces generated from the applied voltage(s) as passed through VLSI circuit interconnect(s). A component computes characteristics of the VLSI interconnect based at least in part upon the measured deflection characteristics.

Vertical Super-Thin Body Semiconductor On Dielectric Wall Devices And Methods Of Their Fabrication

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US Patent:
20170186882, Jun 29, 2017
Filed:
Dec 12, 2016
Appl. No.:
15/375630
Inventors:
- Dublin CA, US
Rimma A. Pirogova - Morgan Hill CA, US
International Classification:
H01L 29/786
H01L 27/11
H01L 27/11524
H01L 27/12
H01L 23/528
Abstract:
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.

Vertical Super-Thin Body Semiconductor On Dielectric Wall Devices And Methods Of Their Fabrication

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US Patent:
20150279997, Oct 1, 2015
Filed:
Jun 3, 2015
Appl. No.:
14/729917
Inventors:
- Dublin CA, US
Rimma A. Pirogova - Morgan Hill CA, US
International Classification:
H01L 29/78
H01L 23/535
H01L 29/06
H01L 27/088
H01L 27/115
Abstract:
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.

Vertical Super-Thin Body Semiconductor On Dielectric Wall Devices And Methods Of Their Fabrication

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US Patent:
20140103414, Apr 17, 2014
Filed:
Jul 11, 2013
Appl. No.:
13/940190
Inventors:
Victor Koldiaev - Morgan Hill CA, US
Rimma Pirogova - Morgan Hill CA, US
International Classification:
H01L 27/092
H01L 27/108
H01L 27/088
US Classification:
257296, 257331, 257369
Abstract:
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.

Vertical Super-Thin Body Semiconductor On Dielectric Wall Devices And Methods Of Their Fabrication

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US Patent:
20140106523, Apr 17, 2014
Filed:
Jul 11, 2013
Appl. No.:
13/940197
Inventors:
Viktor Koldiaev - Morgan Hill CA, US
Rimma Pirogova - Morgan Hill CA, US
International Classification:
H01L 21/8238
US Classification:
438212
Abstract:
The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.
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Rimma A Pirogova from San Jose, CA, age ~76 Get Report