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Alper Yonca Ilkbahar

from Los Gatos, CA
Age ~57
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Also known as:
Alper Yonka Ilkbahar, Ilkbahanr Alper, Alber Ilbahar
Phone and address:
17259 Deer Park Rd, Los Gatos, CA 95032
(408) 356-5954
Related to:
Aysen Ilkbahar, 46Ilkbahar Alper, 57Yonca N Ilkbahar, 57Yonca IlkbaharAysen Ilkbahar
Connected to:
Larry D Ilkenhans, 58Mavis K Ilkenhans, 80Trent W Ilkenhans, 52Yuri Ilkevitch, 63Fatemeh Ilkhan, 105David H Ilkhani, 44Erhan Ilkmen, 47Igor Ilkovski, 40Ariadne A Ill, 72Dennis Ill, 80

Alper Ilkbahar Phones & Addresses

  • 17259 Deer Park Rd, Los Gatos, CA 95032 (408) 356-5954
  • San Jose, CA
  • Ann Arbor, MI
  • Santa Cruz, CA
  • Santa Clara, CA

Work

Company: Intel corporation Sep 1, 2016 Position: Vice president and general manager, data center memory and storage solutions

Education

School / High School: Wharton School of Business

Skills

Semiconductors • Electronics • 3D Graphics • Science • Engineering • Nand • Technology Development

Languages

Turkish • German

Industries

Semiconductors

Resumes

Resumes

Alper Ilkbahar Photo 1

Vice President And General Manager, Data Center Memory And Storage Solutions

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Location:
Milpitas, CA
Industry:
Semiconductors
Work:
Intel Corporation
Vice President and General Manager, Data Center Memory and Storage Solutions
Sandisk 2015 - Sep 2016
Vice President and General Manager - Storage Class Memory Solutions
Sandisk 2014 - 2015
Vice President of Marketing - Enterprise Storage Solutions
Sandisk 2011 - 2014
Vice President and General Manager - Connected and Computing Solutions
Sandisk 2008 - 2011
Vice President and General Manager - Wafer and Components Business
Education:
Wharton School of Business
The Wharton School
Master of Business Administration, Masters University of Michigan
Master of Science, Masters, Electronics Engineering Boğaziçi University
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Semiconductors
Electronics
3D Graphics
Science
Engineering
Nand
Technology Development
Languages:
Turkish
German

Publications

Us Patents

Memory Cell That Includes A Carbon-Based Memory Element And Methods Of Forming The Same

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US Patent:
20120119178, May 17, 2012
Filed:
Jan 17, 2012
Appl. No.:
13/351468
Inventors:
Roy E. Scheuerlein - Cupertino CA, US
Alper Ilkbahar - San Jose CA, US
April D. Schricker - Palo Alto CA, US
International Classification:
H01L 45/00
H01L 21/8239
US Classification:
257 2, 438382, 257E21004, 257E21645
Abstract:
In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.

Three-Dimensional Memory Device Incorporating Segmented Array Line Memory Array

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US Patent:
20120106253, May 3, 2012
Filed:
Jan 11, 2012
Appl. No.:
13/348336
Inventors:
Roy E. Scheuerlein - Cupertino CA, US
Alper Ilkbahar - San Jose CA, US
Luca Fasoli - San Jose CA, US
International Classification:
G11C 5/06
G11C 16/04
US Classification:
36518513, 365 63
Abstract:
A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

Carbon-Based Resistivity-Switching Materials And Methods Of Forming The Same

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US Patent:
20100006812, Jan 14, 2010
Filed:
Jul 8, 2009
Appl. No.:
12/499467
Inventors:
Huiwen Xu - Sunnyvale CA, US
Xiying Chen - San Jose CA, US
Roy E. Scheuerlein - Cupertino CA, US
Er-Xuan Ping - Fremont CA, US
Tanmay Kumar - Pleasanton CA, US
Alper Ilkbahar - San Jose CA, US
Assignee:
SanDisk 3D LLC - Milpitas CA
International Classification:
H01L 29/02
H01L 21/00
US Classification:
257 2, 438485, 977773, 257E29006, 257E21001
Abstract:
Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.

Memory Cell That Includes A Carbon-Based Memory Element And Methods Of Forming The Same

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US Patent:
20090256132, Oct 15, 2009
Filed:
Apr 6, 2009
Appl. No.:
12/418855
Inventors:
Roy E. Scheuerlein - Cupertino CA, US
Alper Ilkbahar - San Jose CA, US
April D. Schricker - Palo Alto CA, US
Assignee:
SanDisk 3D LLC - Milpitas CA
International Classification:
H01L 47/00
H01L 21/365
US Classification:
257 4, 438478, 438509, 257E47005, 257E47001, 257E21463
Abstract:
In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

Method Of Making Nonvolatile Memory Cell Containing Carbon Resistivity Switching As A Storage Element By Low Temperature Processing

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US Patent:
20090258135, Oct 15, 2009
Filed:
Aug 7, 2008
Appl. No.:
12/222341
Inventors:
Tanmay Kumar - Pleasanton CA, US
Er-Xuan Ping - Fremont CA, US
Alper Ilkbahar - San Jose CA, US
International Classification:
B05D 5/12
US Classification:
427122
Abstract:
A method of making a nonvolatile memory cell includes forming a steering element and forming a carbon resistivity switching material storage element by coating a carbon containing colloid.

Method And Apparatus For Improving Yield In Semiconductor Devices By Guaranteeing Health Of Redundancy Information

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US Patent:
20070291563, Dec 20, 2007
Filed:
Aug 21, 2007
Appl. No.:
11/894861
Inventors:
Alper Ilkbahar - San Jose CA, US
Derek Bosch - Mountain View CA, US
International Classification:
G11C 29/04
US Classification:
365201000
Abstract:
A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

Nand Memory Array Incorporating Capacitance Boosting Of Channel Regions In Unselected Memory Cells And Method For Operation Of Same

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US Patent:
20070242511, Oct 18, 2007
Filed:
Jun 18, 2007
Appl. No.:
11/764793
Inventors:
Andrew Walker - Mountain View CA, US
Roy Scheuerlein - Cupertino CA, US
Sucheta Nallamothu - San Jose CA, US
Alper Ilkbahar - San Jose CA, US
Luca Fasoli - San Jose CA, US
International Classification:
G11C 16/10
US Classification:
365185020
Abstract:
An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Method And Apparatus For Improving Yield In Semiconductor Devices By Guaranteeing Health Of Redundancy Information

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US Patent:
20060140026, Jun 29, 2006
Filed:
Dec 28, 2004
Appl. No.:
11/024516
Inventors:
Alper Ilkbahar - San Jose CA, US
Derek Bosch - Mountain View CA, US
International Classification:
G11C 29/00
US Classification:
365200000
Abstract:
A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.
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Alper Yonca Ilkbahar from Los Gatos, CA, age ~57 Get Report