Kenneth S Goekjian

20050223131, Oct 6, 2005

Apr 2, 2004

10/817207

Kenneth Goekjian - Candia NH, US
Raymond Cacciatore - Westford MA, US

G06F013/28

710022000

A direct memory access (DMA) system provides a single context-based DMA engine connected to the memory system. The context-based DMA Engine implements the logic for each DMA function only once, and switches parameter sets as needed to service various DMA requests from different channels. Arbitration is performed at the DMA request level. After a DMA channel is selected for service, the parameters for that channel's transfer are retrieved from a central context block, the data transfer is queued to the memory system, and the parameters are updated and stored back to the central context block. Data paths also are constructed to support context-based transfer, using buffer blocks, to allow the DMA engine and the memory system to access any channel's data through simple addressing of the buffer block. A buffer control unit allows independent flow control between write and read DMA channels accessing the same data, preventing underflow or overflow of data during simultaneous DMA operations.

48781738, Oct 31, 1989

May 16, 1988

7/194685

Kenneth S. Goekjian - Candia NH

Data General Corporation - Westboro MA

G06F 300

364200

A data processing system in which the interface for connecting a host controller to a burst multiplexor channel comprises two sections one to handle the transfer of data and the other to handle the transfer of command and status information. The interface also includes logic to monitor the division of any transfer into bursts and logic to arbitrate for the two sections for any given burst.

52356850, Aug 10, 1993

May 11, 1989

7/350331

Stephen A. Caldara - Sudbury MA
John R. McDaniel - Rochester NH
Kenneth S. Goekjian - Candia NH
Donald J. Barbarits - Durham NH
Salvatore Faletra - Somersworth NH
John E. Shur - Stratham NH

Data General Corp. - Westboro MA

G06F 1300

395325

A data processing system is disclosed in which a plurality of high performance, intelligent, mass storage input-output devices are linked to a host controller by an input-output interface bus which is divided into three sections. Each section is completely independent of the other two sections and used for a different and specific purpose. One section is used to transfer commands and retrieve status information. A second section is used to handle device requests for data transfer and device signals for operation complete. The third section is used to transfer data to and from a device. Since the three sections are completely independent, simultaneous transfer of command control and data to different input-output devices or to a single input-output device can be performed.